7c2c8d8e56
Move a copy of the PLIC driver out of one of the platforms and make the setup of the interrupt controller a bit more dynamic.
47 lines
1.2 KiB
C
47 lines
1.2 KiB
C
/*
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* Copyright (c) 2018 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#pragma once
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#define SIFIVE_IRQ_WATCHDOG 1
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#define SIFIVE_IRQ_RTC 2
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#define SIFIVE_IRQ_UART0 3
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#define SIFIVE_IRQ_UART1 4
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#define SIFIVE_IRQ_QSPI0 5
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#define SIFIVE_IRQ_QSPI1 6
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#define SIFIVE_IRQ_QSPI2 7
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#define SIFIVE_IRQ_GPIO_BASE 8
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#define SIFIVE_IRQ_GPIO(n) (SIFIVE_IRQ_GPIO_BASE+(n))
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#define SIFIVE_IRQ_PWM_BASE 40
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#define SIFIVE_NUM_IRQS 64
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#define CLINT_BASE 0x02000000
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#define PLIC_BASE 0x0c000000
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#define AON_BASE 0x10000000
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#define PRCI_BASE 0x10008000
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#define OTP_BASE 0x10010000
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#define GPIO_BASE 0x10012000
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#define UART0_BASE 0x10013000
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#define QSPI0_BASE 0x10014000
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#define PWM0_BASE 0x10015000
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#define UART1_BASE 0x10023000
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#define QSPI1_BASE 0x10024000
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#define PWM1_BASE 0x10025000
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#define QSPI2_BASE 0x10034000
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#define PWM2_BASE 0x10035000
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#define GPIO_REG_VALUE 0
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#define GPIO_REG_INPUT_EN 1
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#define GPIO_REG_OUTPUT_EN 2
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#define GPIO_REG_PORT 3
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#define GPIO_REG_IOF_EN 14
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#define GPIO_REG_IOF_SEL 15
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#define GPIO_AF0 (1U << 16)
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#define GPIO_AF1 (1U << 17)
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