Travis Geiselbrecht 763adc65c5 [arch][arm] fix cache disable routines ...

-Make sure the stack is kept 8 byte aligned during flush routines
-Properly save and restore cpsr during cache disable
-in PL310, spin on the control register until the disable bit sticks

2014-08-12 16:06:18 -07:00

..

include/dev/cache

[dev][cache] initial implementation of PL310 cache controller

2014-06-03 21:16:46 -07:00

pl310.c

[arch][arm] fix cache disable routines

2014-08-12 16:06:18 -07:00

rules.mk

[dev][cache] initial implementation of PL310 cache controller

2014-06-03 21:16:46 -07:00