Travis Geiselbrecht 763adc65c5 [arch][arm] fix cache disable routines ...

-Make sure the stack is kept 8 byte aligned during flush routines
-Properly save and restore cpsr during cache disable
-in PL310, spin on the control register until the disable bit sticks

2014-08-12 16:06:18 -07:00

..

cache/pl310

[arch][arm] fix cache disable routines

2014-08-12 16:06:18 -07:00

class

[dev] Add netif class API.

2013-07-18 02:30:41 -07:00

fbcon

[dev] run astyle on dev/

2012-10-31 21:53:43 -07:00

interrupt/arm_gic

[platform][zynq] switch to the GIC driver for interrupt controller business

2014-05-01 19:06:50 -07:00

keys

[dev] run astyle on dev/

2012-10-31 21:53:43 -07:00

net/smc91c96

[libc][stdio] cleanup printf definition and clients

2013-08-05 10:04:29 -07:00

pmic/twl4030

[libc] move tracing out of debug into separate trace.h

2013-08-05 10:04:29 -07:00

timer/arm_cortex_a9

[dev][timer] add generic cortex-a9 timer driver

2014-05-11 00:45:15 -07:00

usb

[dev][usb] more usb stack cleanup

2013-10-20 16:04:13 -07:00

virtio

[dev][virtio] patch up to work in the post-vm world

2014-07-24 01:55:05 -07:00

dev.c

initial commit of lk (little kernel) project

2008-09-01 02:26:09 -07:00

driver.c

[libc] move tracing out of debug into separate trace.h

2013-08-05 10:04:29 -07:00

rules.mk

[dev] Add netif class API.

2013-07-18 02:30:41 -07:00