208 lines
6.2 KiB
C
208 lines
6.2 KiB
C
/*
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* Copyright (c) 2014 Travis Geiselbrecht
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files
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* (the "Software"), to deal in the Software without restriction,
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* including without limitation the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dev/cache/pl310.h>
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#include <assert.h>
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#include <trace.h>
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#include <err.h>
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#include <reg.h>
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#include <arch.h>
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#include <arch/arm/mmu.h>
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#include <dev/cache/pl310_config.h>
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#include <lk/init.h>
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/* configuration of the pl310 comes from #define space */
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#ifndef PL310_BASE
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#error need to define PL310_BASE
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#endif
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#define LOCAL_TRACE 0
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#define PL310_REG(reg) (*REG32(PL310_BASE + (reg)))
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/* registers */
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#define REG0_CACHE_ID 0x000
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#define REG0_CACHE_TYPE 0x004
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#define REG1_CONTROL 0x100
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#define REG1_AUX_CONTROL 0x104
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#define REG1_TAG_RAM_CONTROL 0x108
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#define REG1_DATA_RAM_CONTROL 0x10c
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#define REG2_EV_COUNTER_CTRL 0x200
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#define REG2_EV_COUNTER1_CFG 0x204
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#define REG2_EV_COUNTER0_CFG 0x208
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#define REG2_EV_COUNTER1 0x20c
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#define REG2_EV_COUNTER0 0x210
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#define REG2_INT_MASK 0x214
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#define REG2_INT_MASK_STATUS 0x218
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#define REG2_INT_RAW_STATUS 0x21c
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#define REG2_INT_CLEAR 0x220
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#define REG7_CACHE_SYNC 0x730
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#define REG7_INV_PA 0x770
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#define REG7_INV_WAY 0x77c
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#define REG7_CLEAN_PA 0x7b0
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#define REG7_CLEAN_INDEX 0x7b8
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#define REG7_CLEAN_WAY 0x7bc
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#define REG7_CLEAN_INV_PA 0x7f0
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#define REG7_CLEAN_INV_INDEX 0x7f8
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#define REG7_CLEAN_INV_WAY 0x7fc
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#define REG9_D_LOCKDOWN0 0x900
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#define REG9_I_LOCKDOWN0 0x904
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#define REG9_D_LOCKDOWN1 0x908
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#define REG9_I_LOCKDOWN1 0x90c
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#define REG9_D_LOCKDOWN2 0x910
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#define REG9_I_LOCKDOWN2 0x914
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#define REG9_D_LOCKDOWN3 0x918
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#define REG9_I_LOCKDOWN3 0x91c
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#define REG9_D_LOCKDOWN4 0x920
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#define REG9_I_LOCKDOWN4 0x924
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#define REG9_D_LOCKDOWN5 0x928
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#define REG9_I_LOCKDOWN5 0x92c
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#define REG9_D_LOCKDOWN6 0x930
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#define REG9_I_LOCKDOWN6 0x934
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#define REG9_D_LOCKDOWN7 0x938
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#define REG9_I_LOCKDOWN7 0x93c
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#define REG9_LOCK_LINE_EN 0x950
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#define REG9_UNLOCK_WAY 0x954
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#define REG12_ADDR_FILTERING_START 0xc00
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#define REG12_ADDR_FILTERING_END 0xc04
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#define REG15_DEBUG_CTRL 0xf40
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#define REG15_PREFETCH_CTRL 0xf60
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#define REG15_POWER_CTRL 0xf80
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static inline bool pl310_enabled(void)
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{
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return !!(PL310_REG(REG1_CONTROL) & 1);
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}
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static void pl310_init(uint level)
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{
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/* make sure it's already disabled */
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DEBUG_ASSERT(!pl310_enabled());
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/* set tag and data ram latency */
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PL310_REG(REG1_TAG_RAM_CONTROL) = PL310_TAG_RAM_LATENCY;
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PL310_REG(REG1_DATA_RAM_CONTROL) = PL310_DATA_RAM_LATENCY;
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/* flush all the ways */
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PL310_REG(REG7_INV_WAY) = 0xffff;
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}
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/* run just before arch_early_init so the L2 is ready to go when
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* the arch code starts up the caching system.
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*/
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LK_INIT_HOOK(pl310_init, pl310_init, LK_INIT_LEVEL_ARCH_EARLY - 1);
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status_t pl310_set_enable(bool enable)
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{
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LTRACEF("enable %d\n", enable);
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if (enable) {
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if ((PL310_REG(REG1_CONTROL) & 1) == 0) {
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/* if disabled */
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PL310_REG(REG1_CONTROL) = 1;
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}
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} else {
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if ((PL310_REG(REG1_CONTROL) & 1) == 1) {
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/* if enabled */
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pl310_flush_invalidate();
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PL310_REG(REG1_CONTROL) = 0;
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/* this seems to not always latch on the first try */
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while (PL310_REG(REG1_CONTROL) & 1) {
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PL310_REG(REG1_CONTROL) = 0;
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}
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}
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}
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return NO_ERROR;
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}
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void pl310_invalidate(void)
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{
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if (unlikely(!pl310_enabled()))
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return;
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PL310_REG(REG7_INV_WAY) = 0xffff;
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while (PL310_REG(REG7_INV_WAY) != 0)
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;
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}
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void pl310_flush_invalidate(void)
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{
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if (unlikely(!pl310_enabled()))
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return;
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PL310_REG(REG7_CLEAN_INV_WAY) = 0xffff;
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while (PL310_REG(REG7_CLEAN_INV_WAY) != 0)
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;
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}
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void pl310_sync_range(void)
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{
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if (unlikely(!pl310_enabled()))
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return;
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PL310_REG(REG7_CACHE_SYNC) = 1;
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}
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#define PL310_LOOP_BODY(reg) \
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if (unlikely(!pl310_enabled())) \
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return; \
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\
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addr_t pa = 0; \
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uint32_t last_pa_page = 1; \
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addr_t last_va = start + len; \
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start &= ~(CACHE_LINE - 1); \
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while (start < last_va) { \
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if (unlikely(pa / PAGE_SIZE != last_pa_page)) { \
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/* get the physical address */ \
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if (unlikely(arm_vtop(start, &pa))) \
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return; \
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last_pa_page = pa / PAGE_SIZE; \
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} \
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PL310_REG(reg) = pa; \
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while (PL310_REG(reg) & 1) \
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; \
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\
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pa += CACHE_LINE; \
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start += CACHE_LINE; \
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} \
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\
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PL310_REG(REG7_CACHE_SYNC) = 1;
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void pl310_clean_range(addr_t start, size_t len)
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{
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LTRACEF("start 0x%lx, len %zd\n", start, len);
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PL310_LOOP_BODY(REG7_CLEAN_PA);
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}
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void pl310_clean_invalidate_range(addr_t start, size_t len)
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{
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LTRACEF("start 0x%lx, len %zd\n", start, len);
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PL310_LOOP_BODY(REG7_CLEAN_INV_PA);
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}
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void pl310_invalidate_range(addr_t start, size_t len)
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{
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LTRACEF("start 0x%lx, len %zd\n", start, len);
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PL310_LOOP_BODY(REG7_INV_PA);
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}
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