6a7c4e25d6
This is a pretty major implementation change of the GIC driver, but it now handles v3. Unfortunately this is a bit of a revert of some of the code cleanups and whatnot that have happened on mainline, but will try to reapply these momentarily. TODO: -fix arm32 and computation of SGI targets for v3 -Consider removing all of the secure mode stuff which is really complicating things and basically untestable in mainline. -Properly split V2 and V3 into separate files, and have the main gic.c act as a redirector of calls. -Allow both v2 and v3 to compile at the same time. -Make configuration runtime configurable, stop using #define GICBASE and others.
346 lines
13 KiB
C
346 lines
13 KiB
C
/*
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* Copyright (c) 2012-2019 LK Trusty Authors. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files
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* (the "Software"), to deal in the Software without restriction,
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* including without limitation the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#pragma once
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#include <platform/gic.h>
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#include <lk/reg.h>
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#if ARCH_ARM
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#include <arch/arm.h>
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#endif
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#if ARCH_ARM64
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#include <arch/arm64.h>
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#endif
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#ifdef ARCH_ARM
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/*
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* AArch32 does not have 64 bit mmio support, but the gic spec allows 32 bit
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* upper and lower access to _most_ 64 bit gic registers (not GICR_VSGIPENDR,
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* GICR_VSGIR or GITS_SGIR).
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*/
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/* TODO: add mmio_read32 when needed */
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static inline void mmio_write64(volatile uint64_t *ptr64, uint64_t val) {
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volatile uint32_t *ptr = (volatile uint32_t *)ptr64;
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mmio_write32(ptr, (uint32_t)val);
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mmio_write32(ptr + 1, val >> 32);
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}
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#endif
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struct arm_gic {
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vaddr_t gicc_vaddr;
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size_t gicc_size;
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vaddr_t gicd_vaddr;
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size_t gicd_size;
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vaddr_t gicr_vaddr;
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size_t gicr_size;
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};
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#define NUM_ARM_GICS 1
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extern struct arm_gic arm_gics[NUM_ARM_GICS];
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#if GIC_VERSION > 2
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#if WITH_LIB_SM
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#define ARM_GIC_USE_DOORBELL_NS_IRQ 1
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#define ARM_GIC_DOORBELL_IRQ 13
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#endif
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/* GICv3/v4 */
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#define GICV3_IRQ_GROUP_GRP0S 0
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#define GICV3_IRQ_GROUP_GRP1NS 1
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#define GICV3_IRQ_GROUP_GRP1S 2
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#ifndef ARM_GIC_SELECTED_IRQ_GROUP
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#define ARM_GIC_SELECTED_IRQ_GROUP GRP1NS
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#endif
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#define COMBINE2(a, b) a ## b
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#define XCOMBINE2(a, b) COMBINE2(a,b)
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#define GICV3_IRQ_GROUP XCOMBINE2(GICV3_IRQ_GROUP_, ARM_GIC_SELECTED_IRQ_GROUP)
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/*
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* In ARMv8 for GICv3/v4, ARM suggest to use system register
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* to access GICC instead of memory map.
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*/
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#ifdef ARCH_ARM64
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#define GICCREG_READ(gic, reg) ARM64_READ_SYSREG(reg)
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#define GICCREG_WRITE(gic, reg, val) ARM64_WRITE_SYSREG(reg, (uint64_t)val)
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#else /* ARCH_ARM64 */
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/* For 32bit mode, use different way to access registers */
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#define GICCREG_READ(gic, reg) COMBINE2(arm_read_,reg)()
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#define GICCREG_WRITE(gic, reg, val) COMBINE2(arm_write_,reg)(val)
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GEN_CP15_REG_FUNCS(icc_ctlr_el1, 0, c12, c12, 4);
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GEN_CP15_REG_FUNCS(icc_pmr_el1, 0, c4, c6, 0);
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GEN_CP15_REG_FUNCS(icc_bpr0_el1, 0, c12, c8, 3);
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GEN_CP15_REG_FUNCS(icc_iar0_el1, 0, c12, c8, 0);
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GEN_CP15_REG_FUNCS(icc_eoir0_el1, 0, c12, c8, 1);
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GEN_CP15_REG_FUNCS(icc_rpr_el1, 0, c12, c11, 3);
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GEN_CP15_REG_FUNCS(icc_hppir0_el1, 0, c12, c8, 2);
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GEN_CP15_REG_FUNCS(icc_bpr1_el1, 0, c12, c12, 3);
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GEN_CP15_REG_FUNCS(icc_iar1_el1, 0, c12, c12, 0);
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GEN_CP15_REG_FUNCS(icc_eoir1_el1, 0, c12, c12, 1);
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GEN_CP15_REG_FUNCS(icc_hppir1_el1, 0, c12, c12, 2);
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GEN_CP15_REG_FUNCS(icc_dir_el1, 0, c12, c11, 1);
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GEN_CP15_REG_FUNCS(icc_sre_el1, 0, c12, c12, 5);
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GEN_CP15_REG_FUNCS(icc_igrpen0_el1, 0, c12, c12, 6);
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GEN_CP15_REG_FUNCS(icc_igrpen1_el1, 0, c12, c12, 7);
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GEN_CP15_REG_FUNCS(icc_ap0r0_el1, 0, c12, c8, 4);
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GEN_CP15_REG_FUNCS(icc_ap0r1_el1, 0, c12, c8, 5);
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GEN_CP15_REG_FUNCS(icc_ap0r2_el1, 0, c12, c8, 6);
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GEN_CP15_REG_FUNCS(icc_ap0r3_el1, 0, c12, c8, 7);
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GEN_CP15_REG_FUNCS(icc_ap1r0_el1, 0, c12, c9, 0);
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GEN_CP15_REG_FUNCS(icc_ap1r1_el1, 0, c12, c9, 1);
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GEN_CP15_REG_FUNCS(icc_ap1r2_el1, 0, c12, c9, 2);
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GEN_CP15_REG_FUNCS(icc_ap1r3_el1, 0, c12, c9, 3);
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GEN_CP15_REG64_FUNCS(icc_sgi1r_el1, 0, c12);
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GEN_CP15_REG64_FUNCS(icc_asgi1r_el1, 1, c12);
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GEN_CP15_REG64_FUNCS(icc_sgi0r_el1, 2, c12);
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#endif /* ARCH_ARM64 */
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#if GICV3_IRQ_GROUP == GICV3_IRQ_GROUP_GRP0S
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#define GICC_PRIMARY_HPPIR icc_hppir0_el1
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#define GICC_PRIMARY_IAR icc_iar0_el1
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#define GICC_PRIMARY_EOIR icc_eoir0_el1
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#define GICC_PRIMARY_SGIR icc_sgi0r_el1
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#else
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#define GICC_PRIMARY_HPPIR icc_hppir1_el1
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#define GICC_PRIMARY_IAR icc_iar1_el1
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#define GICC_PRIMARY_EOIR icc_eoir1_el1
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#define GICC_PRIMARY_SGIR icc_sgi1r_el1
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#endif
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#define GICC_LIMIT (0x0000)
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#else /* GIC_VERSION > 2 */
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#ifndef GICC_OFFSET
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#define GICC_OFFSET (0x0000)
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#endif
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#define GICCREG_READ(gic, reg) ({ \
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ASSERT(gic < NUM_ARM_GICS); \
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ASSERT(reg >= GICC_OFFSET); \
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ASSERT(reg < GICC_LIMIT); \
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mmio_read32((volatile uint32_t *)(arm_gics[(gic)].gicc_vaddr + ((reg) - GICC_OFFSET))); \
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})
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#define GICCREG_WRITE(gic, reg, val) ({ \
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ASSERT(gic < NUM_ARM_GICS); \
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ASSERT(reg >= GICC_OFFSET); \
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ASSERT(reg < GICC_LIMIT); \
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mmio_write32((volatile uint32_t *)(arm_gics[(gic)].gicc_vaddr + ((reg) - GICC_OFFSET)), (val)); \
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})
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/* main cpu regs */
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#define GICC_CTLR (GICC_OFFSET + 0x0000)
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#define GICC_PMR (GICC_OFFSET + 0x0004)
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#define GICC_BPR (GICC_OFFSET + 0x0008)
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#define GICC_IAR (GICC_OFFSET + 0x000c)
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#define GICC_EOIR (GICC_OFFSET + 0x0010)
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#define GICC_RPR (GICC_OFFSET + 0x0014)
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#define GICC_HPPIR (GICC_OFFSET + 0x0018)
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#define GICC_ABPR (GICC_OFFSET + 0x001c)
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#define GICC_AIAR (GICC_OFFSET + 0x0020)
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#define GICC_AEOIR (GICC_OFFSET + 0x0024)
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#define GICC_AHPPIR (GICC_OFFSET + 0x0028)
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#define GICC_APR(n) (GICC_OFFSET + 0x00d0 + (n) * 4)
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#define GICC_NSAPR(n) (GICC_OFFSET + 0x00e0 + (n) * 4)
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#define GICC_IIDR (GICC_OFFSET + 0x00fc)
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#if 0 /* GICC_DIR is not currently used by anything */
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#define GICC_DIR (GICC_OFFSET + 0x1000)
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#endif
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#define GICC_LIMIT (GICC_OFFSET + 0x1000)
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#define GICC_MIN_SIZE (GICC_LIMIT - GICC_OFFSET)
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#if WITH_LIB_SM
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#define GICC_PRIMARY_HPPIR GICC_AHPPIR
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#define GICC_PRIMARY_IAR GICC_AIAR
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#define GICC_PRIMARY_EOIR GICC_AEOIR
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#else
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#define GICC_PRIMARY_HPPIR GICC_HPPIR
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#define GICC_PRIMARY_IAR GICC_IAR
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#define GICC_PRIMARY_EOIR GICC_EOIR
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#endif
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#endif /* GIC_VERSION > 2 */
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#ifndef GICD_OFFSET
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#define GICD_OFFSET (GICC_LIMIT)
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#endif
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#define GICDREG_READ(gic, reg) ({ \
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ASSERT(gic < NUM_ARM_GICS); \
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ASSERT(reg >= GICD_OFFSET); \
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ASSERT(reg < GICD_LIMIT); \
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mmio_read32((volatile uint32_t *)(arm_gics[(gic)].gicd_vaddr + ((reg) - GICD_OFFSET))); \
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})
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#define GICDREG_WRITE(gic, reg, val) ({ \
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ASSERT(gic < NUM_ARM_GICS); \
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ASSERT(reg >= GICD_OFFSET); \
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ASSERT(reg < GICD_LIMIT); \
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LTRACEF_LEVEL(3, "GICDREG_WRITE base vaddr %#lx gic %d reg 0x%x val 0x%x\n", arm_gics[gic].gicd_vaddr, gic, reg, val); \
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LTRACEF_LEVEL(3, "final address = %#lx\n", arm_gics[gic].gicd_vaddr + ((reg) - GICD_OFFSET)); \
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mmio_write32((volatile uint32_t *)(arm_gics[(gic)].gicd_vaddr + ((reg) - GICD_OFFSET)), (val)); \
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})
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/* distribution regs */
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#define GICD_CTLR (GICD_OFFSET + 0x000)
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#define GICD_TYPER (GICD_OFFSET + 0x004)
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#define GICD_IIDR (GICD_OFFSET + 0x008)
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#define GICD_IGROUPR(n) (GICD_OFFSET + 0x080 + (n) * 4)
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#define GICD_ISENABLER(n) (GICD_OFFSET + 0x100 + (n) * 4)
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#define GICD_ICENABLER(n) (GICD_OFFSET + 0x180 + (n) * 4)
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#define GICD_ISPENDR(n) (GICD_OFFSET + 0x200 + (n) * 4)
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#define GICD_ICPENDR(n) (GICD_OFFSET + 0x280 + (n) * 4)
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#define GICD_ISACTIVER(n) (GICD_OFFSET + 0x300 + (n) * 4)
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#define GICD_ICACTIVER(n) (GICD_OFFSET + 0x380 + (n) * 4)
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#define GICD_IPRIORITYR(n) (GICD_OFFSET + 0x400 + (n) * 4)
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#define GICD_ITARGETSR(n) (GICD_OFFSET + 0x800 + (n) * 4)
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#define GICD_ICFGR(n) (GICD_OFFSET + 0xc00 + (n) * 4)
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#define GICD_NSACR(n) (GICD_OFFSET + 0xe00 + (n) * 4)
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#define GICD_SGIR (GICD_OFFSET + 0xf00)
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#define GICD_CPENDSGIR(n) (GICD_OFFSET + 0xf10 + (n) * 4)
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#define GICD_SPENDSGIR(n) (GICD_OFFSET + 0xf20 + (n) * 4)
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#if GIC_VERSION <= 2
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/* for v3 and higher, these are defined later */
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#define GICD_LIMIT (GICD_OFFSET + 0x1000)
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#define GICD_MIN_SIZE (GICD_LIMIT - GICD_OFFSET)
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#endif /* GIC_VERSION <= 2 */
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/* GICD_CTRL Register
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* Non-Secure Only_a_Single two_Security
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* (1U << 8) RES0 nASSGIreq RES0
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* (1U << 7) RES0 E1NWF E1NWF
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* (1U << 5) RES0 RES0 ARE_NS
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* (1U << 4) ARE_NS ARE ARE_S
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* (1U << 2) RES0 RES0 ENABLE_G1S
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* (1U << 1) ENABLE_G1A ENABLE_G1 ENABLE_G1NS
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* (1U << 0) ENABLE_G1 ENABLE_G0 ENABLE_G0
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*/
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#define GICD_CTLR_RWP (1U << 31)
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#define GICD_CTLR_nASSGIreq (1U << 8)
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#define GICD_CTRL_E1NWF (1U << 7)
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#define GICD_CTLR_DS (1U << 6)
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#define GICD_CTLR_ARE_NS (1U << 5)
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#define GICD_CTLR_ARE_S (1U << 4)
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#define GICD_CTLR_ENABLE_G1S (1U << 2)
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#define GICD_CTLR_ENABLE_G1NS (1U << 1)
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#define GICD_CTLR_ENABLE_G0 (1U << 0)
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#if GIC_VERSION > 2
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/* some registers of GICD are 64 bit */
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#define GICDREG_READ64(gic, reg) ({ \
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ASSERT(gic < NUM_ARM_GICS); \
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ASSERT(reg >= GICD_OFFSET); \
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ASSERT(reg < GICD_LIMIT); \
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mmio_read64((volatile uint64_t *)(arm_gics[(gic)].gicd_vaddr + ((reg) - GICD_OFFSET))); \
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})
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#define GICDREG_WRITE64(gic, reg, val) ({ \
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ASSERT(gic < NUM_ARM_GICS); \
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ASSERT(reg >= GICD_OFFSET); \
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ASSERT(reg < GICD_LIMIT); \
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mmio_write64((volatile uint64_t *)(arm_gics[(gic)].gicd_vaddr + ((reg) - GICD_OFFSET)), (val)); \
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})
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/* GICv3/v4 Distributor interface */
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#define GICD_STATUSR (GICD_OFFSET + 0x0010)
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#define GICD_SETSPI_NSR (GICD_OFFSET + 0x0040)
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#define GICD_CLRSPI_NSR (GICD_OFFSET + 0x0048)
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#define GICD_SETSPI_SR (GICD_OFFSET + 0x0050)
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#define GICD_CLRSPI_SR (GICD_OFFSET + 0x0058)
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#define GICD_IGRPMODR(n) (GICD_OFFSET + 0x0D00 + (n) * 4)
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#define GICD_IROUTER(n) (GICD_OFFSET + 0x6000 + (n) * 8)
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#define GICD_CIDR0 (GICD_OFFSET + 0xfff0)
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#define GICD_CIDR1 (GICD_OFFSET + 0xfff4)
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#define GICD_CIDR2 (GICD_OFFSET + 0xfff8)
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#define GICD_CIDR3 (GICD_OFFSET + 0xfffc)
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#define GICD_PIDR0 (GICD_OFFSET + 0xffe0)
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#define GICD_PIDR1 (GICD_OFFSET + 0xffe4)
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#define GICD_PIDR2 (GICD_OFFSET + 0xffe8)
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#define GICD_PIDR3 (GICD_OFFSET + 0xffec)
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#define GICD_LIMIT (GICD_OFFSET + 0x10000)
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#define GICD_MIN_SIZE (GICD_LIMIT - GICD_OFFSET)
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/* GICv3/v4 Redistrubutor interface */
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#if GIC_VERSION == 3
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#define GICR_CPU_OFFSET(cpu) ((cpu) * 0x20000)
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#endif
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#if GIC_VERSION == 4
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#define GICR_CPU_OFFSET(cpu) ((cpu) * 0x40000)
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#endif
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#ifndef GICR_OFFSET
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#define GICR_OFFSET (GICD_LIMIT)
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#endif
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#define GICRREG_READ(gic, cpu, reg) ({ \
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ASSERT(gic < NUM_ARM_GICS); \
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ASSERT(cpu < SMP_MAX_CPUS); \
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ASSERT(reg >= GICR_OFFSET); \
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ASSERT(reg < GICR_LIMIT); \
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mmio_read32((volatile uint32_t *)(arm_gics[(gic)].gicr_vaddr + GICR_CPU_OFFSET(cpu) + ((reg) - GICR_OFFSET))); \
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})
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#define GICRREG_WRITE(gic, cpu, reg, val) ({ \
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ASSERT(gic < NUM_ARM_GICS); \
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ASSERT(cpu < SMP_MAX_CPUS); \
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ASSERT(reg >= GICR_OFFSET); \
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ASSERT(reg < GICR_LIMIT); \
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LTRACEF_LEVEL(3, "GICRREG_WRITE base vaddr %#lx gic %d cpu %d reg 0x%x val 0x%x\n", arm_gics[gic].gicr_vaddr, gic, cpu, reg, val); \
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LTRACEF_LEVEL(3, "final address = %#lx\n", arm_gics[gic].gicr_vaddr + GICR_CPU_OFFSET(cpu) + ((reg) - GICR_OFFSET)); \
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mmio_write32((volatile uint32_t *)(arm_gics[(gic)].gicr_vaddr + GICR_CPU_OFFSET(cpu) + ((reg) - GICR_OFFSET)), (val)); \
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})
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#define GICR_CTRL (GICR_OFFSET + 0x0000)
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#define GICR_IIDR (GICR_OFFSET + 0x0004)
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#define GICR_TYPER (GICR_OFFSET + 0x0008)
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#define GICR_STATUSR (GICR_OFFSET + 0x0010)
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#define GICR_WAKER (GICR_OFFSET + 0x0014)
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/* The following GICR registers are on separate 64KB page */
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#define GICR_SGI_OFFSET (GICR_OFFSET + 0x10000)
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#define GICR_IGROUPR0 (GICR_SGI_OFFSET + 0x0080)
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#define GICR_ISENABLER0 (GICR_SGI_OFFSET + 0x0100)
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#define GICR_ICENABLER0 (GICR_SGI_OFFSET + 0x0180)
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#define GICR_ISPENDR0 (GICR_SGI_OFFSET + 0x0200)
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#define GICR_ICPENDR0 (GICR_SGI_OFFSET + 0x0280)
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#define GICR_ISACTIVER0 (GICR_SGI_OFFSET + 0x0300)
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#define GICR_ICACTIVER0 (GICR_SGI_OFFSET + 0x0380)
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#define GICR_IPRIORITYR(n) (GICR_SGI_OFFSET + 0x0400 + (n) * 4)
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#define GICR_ICFGR(n) (GICR_SGI_OFFSET + 0x0C00 + (n) * 4)
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#define GICR_IGRPMODR0 (GICR_SGI_OFFSET + 0x0D00)
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#define GICR_NSACR (GICR_SGI_OFFSET + 0x0E00)
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#define GICR_LIMIT (GICR_SGI_OFFSET + 0x1000)
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#define GICR_MIN_SIZE (0x10000)
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#endif /* GIC_VERSION > 2 */
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// XXX: from trusty macros.h
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#define ROUND_UP(n, d) (((n) + (size_t)(d) - 1) & ~((size_t)(d) - 1))
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#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
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