d06fbd35c8
The port more or less fully works now, except for actual interrupt driven io and proper atomics. Also hit a floating point exception in the string benchmark.
116 lines
3.6 KiB
C
116 lines
3.6 KiB
C
/*
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* Copyright (c) 2019 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include <assert.h>
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#include <lk/compiler.h>
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#include <lk/debug.h>
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#include <lk/trace.h>
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#include <stdint.h>
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#include <arch/ops.h>
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#include <arch/vax.h>
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#include <kernel/thread.h>
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#define LOCAL_TRACE 0
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// initial boot stack that start.S leaves us on
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extern uint8_t boot_stack[1024];
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static uint8_t irq_stack[512] __ALIGNED(4);
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// defined in assembly
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extern uint32_t SCB[];
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extern void vax_undefined_exception(void);
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extern void vax_exception_table(void);
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static void dump_pr(const char *name, int reg) {
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printf("%s\t%#x\n", name, mfpr(reg));
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}
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#define dump_pr_byname(name) \
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dump_pr(#name, PR_##name)
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static void dump_regs(void) {
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dump_pr_byname(SID);
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dump_pr_byname(KSP); // Kernel Stack Pointer
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dump_pr_byname(ESP); // Executive Stack Pointer
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dump_pr_byname(SSP); // Supervisor Stack Pointer
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dump_pr_byname(USP); // User Stack Pointer
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dump_pr_byname(ISP); // Interrupt Stack Pointer
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dump_pr_byname(P0BR); // P0 Base Register
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dump_pr_byname(P0LR); // P0 Length Register
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dump_pr_byname(P1BR); // P1 Base Register
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dump_pr_byname(P1LR); // P1 Length Register
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dump_pr_byname(SBR); // System Base Register
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dump_pr_byname(SLR); // System Limit Register
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dump_pr_byname(PCBB); // Process Control Block Base
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dump_pr_byname(SCBB); // System Control Block Base
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dump_pr_byname(IPL); // Interrupt Priority Level
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dump_pr_byname(MAPEN); // Memory Management Enable
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}
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void arch_early_init(void) {
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// initialize any empty slots in the SCB
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for (int i = 0; i < SCB_MAX_OFFSET / 4; i++) {
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if (SCB[i] == 0) {
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SCB[i] = ((uint32_t)&vax_exception_table + (i * 16)) | SCB_FLAG_KERNEL_STACK;
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}
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}
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mtpr((uint32_t)SCB, PR_SCBB);
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// point the pcb base register at the bootstrap thread's empty pcb.
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// we'll switch from it later when starting the threading system.
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mtpr((uint32_t)&get_current_thread()->arch.pcb, PR_PCBB);
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get_current_thread()->arch.pcb.p0lr = (4<<24); // set the AST level to 4
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// set the interrupt stack. currently unused, but set it to something safe for now.
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mtpr((uint32_t)irq_stack + sizeof(irq_stack), PR_ISP);
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// null out the mmu registers
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mtpr(0, PR_MAPEN);
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mtpr(0, PR_SBR);
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mtpr(0, PR_SLR);
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mtpr(0, PR_P0BR);
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mtpr(0, PR_P0LR);
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mtpr(0, PR_P1BR);
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mtpr(0, PR_P1LR);
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dump_regs();
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}
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void arch_init(void) {
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// print some arch info
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//dprintf(INFO, "RISCV: mvendorid %#lx marchid %#lx mimpid %#lx mhartid %#lx\n",
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// riscv_csr_read(mvendorid), riscv_csr_read(marchid),
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// riscv_csr_read(mimpid), riscv_csr_read(mhartid));
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//dprintf(INFO, "RISCV: misa %#lx\n", riscv_csr_read(misa));
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// enable external interrupts
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//riscv_csr_set(mie, RISCV_MIE_MEIE);
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}
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void arch_idle(void) {
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// __asm__ volatile("wfi");
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}
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void arch_chain_load(void *entry, ulong arg0, ulong arg1, ulong arg2, ulong arg3) {
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PANIC_UNIMPLEMENTED;
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}
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/* unimplemented cache operations */
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void arch_disable_cache(uint flags) { PANIC_UNIMPLEMENTED; }
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void arch_enable_cache(uint flags) { PANIC_UNIMPLEMENTED; }
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void arch_clean_cache_range(addr_t start, size_t len) { PANIC_UNIMPLEMENTED; }
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void arch_clean_invalidate_cache_range(addr_t start, size_t len) { PANIC_UNIMPLEMENTED; }
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void arch_invalidate_cache_range(addr_t start, size_t len) { PANIC_UNIMPLEMENTED; }
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void arch_sync_cache_range(addr_t start, size_t len) { PANIC_UNIMPLEMENTED; }
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