664bb17afa
- X86 cpuid feature list dump was using the wrong array and walking off the end of one. - GICv2 code had a left shift by up to 31 of an integer. Needs to be unsigned. - PLIC same as GIC code. - fdtwalker code should be using a bytewise accessor based helper function for reading large integers out of an unaliged FDT. - PCI BIOS32 search code could do a 32bit unaligned read of a string, switch to using memcmp.
645 lines
20 KiB
C
645 lines
20 KiB
C
/*
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* Copyright (c) 2012-2015 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include <assert.h>
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#include <lk/bits.h>
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#include <lk/err.h>
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#include <sys/types.h>
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#include <lk/debug.h>
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#include <dev/interrupt/arm_gic.h>
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#include <lk/reg.h>
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#include <kernel/thread.h>
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#include <kernel/debug.h>
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#include <lk/init.h>
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#include <platform/interrupts.h>
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#include <arch/ops.h>
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#include <platform/gic.h>
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#include <lk/trace.h>
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#if WITH_LIB_SM
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#include <lib/sm.h>
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#include <lib/sm/sm_err.h>
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#endif
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#define LOCAL_TRACE 0
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#if ARCH_ARM
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#include <arch/arm.h>
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#define iframe arm_iframe
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#define IFRAME_PC(frame) ((frame)->pc)
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#endif
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#if ARCH_ARM64
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#include <arch/arm64.h>
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#define iframe arm64_iframe_short
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#define IFRAME_PC(frame) ((frame)->elr)
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#endif
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static status_t arm_gic_set_secure_locked(u_int irq, bool secure);
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static spin_lock_t gicd_lock;
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#if WITH_LIB_SM
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#define GICD_LOCK_FLAGS SPIN_LOCK_FLAG_IRQ_FIQ
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#else
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#define GICD_LOCK_FLAGS SPIN_LOCK_FLAG_INTERRUPTS
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#endif
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#define GIC_MAX_PER_CPU_INT 32
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#if WITH_LIB_SM
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static bool arm_gic_non_secure_interrupts_frozen;
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static bool arm_gic_interrupt_change_allowed(uint irq) {
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if (!arm_gic_non_secure_interrupts_frozen)
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return true;
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TRACEF("change to interrupt %u ignored after booting ns\n", irq);
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return false;
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}
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static void suspend_resume_fiq(bool resume_gicc, bool resume_gicd);
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#else
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static bool arm_gic_interrupt_change_allowed(uint irq) {
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return true;
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}
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static void suspend_resume_fiq(bool resume_gicc, bool resume_gicd) {
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}
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#endif
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struct int_handler_struct {
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int_handler handler;
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void *arg;
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};
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static struct int_handler_struct int_handler_table_per_cpu[GIC_MAX_PER_CPU_INT][SMP_MAX_CPUS];
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static struct int_handler_struct int_handler_table_shared[MAX_INT-GIC_MAX_PER_CPU_INT];
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static struct int_handler_struct *get_int_handler(unsigned int vector, uint cpu) {
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if (vector < GIC_MAX_PER_CPU_INT) {
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return &int_handler_table_per_cpu[vector][cpu];
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} else {
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return &int_handler_table_shared[vector - GIC_MAX_PER_CPU_INT];
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}
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}
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void register_int_handler(unsigned int vector, int_handler handler, void *arg) {
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struct int_handler_struct *h;
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uint cpu = arch_curr_cpu_num();
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spin_lock_saved_state_t state;
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if (vector >= MAX_INT)
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panic("register_int_handler: vector out of range %d\n", vector);
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spin_lock_save(&gicd_lock, &state, GICD_LOCK_FLAGS);
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if (arm_gic_interrupt_change_allowed(vector)) {
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h = get_int_handler(vector, cpu);
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h->handler = handler;
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h->arg = arg;
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}
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spin_unlock_restore(&gicd_lock, state, GICD_LOCK_FLAGS);
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}
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void register_int_handler_msi(unsigned int vector, int_handler handler, void *arg, bool edge) {
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// only can deal with edge triggered at the moment
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DEBUG_ASSERT(edge);
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register_int_handler(vector, handler, arg);
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}
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/* main cpu regs */
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#define GICC_CTLR (GICC_OFFSET + 0x0000)
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#define GICC_PMR (GICC_OFFSET + 0x0004)
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#define GICC_BPR (GICC_OFFSET + 0x0008)
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#define GICC_IAR (GICC_OFFSET + 0x000c)
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#define GICC_EOIR (GICC_OFFSET + 0x0010)
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#define GICC_RPR (GICC_OFFSET + 0x0014)
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#define GICC_HPPIR (GICC_OFFSET + 0x0018)
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#define GICC_APBR (GICC_OFFSET + 0x001c)
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#define GICC_AIAR (GICC_OFFSET + 0x0020)
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#define GICC_AEOIR (GICC_OFFSET + 0x0024)
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#define GICC_AHPPIR (GICC_OFFSET + 0x0028)
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#define GICC_APR(n) (GICC_OFFSET + 0x00d0 + (n) * 4)
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#define GICC_NSAPR(n) (GICC_OFFSET + 0x00e0 + (n) * 4)
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#define GICC_IIDR (GICC_OFFSET + 0x00fc)
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#define GICC_DIR (GICC_OFFSET + 0x1000)
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/* distribution regs */
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#define GICD_CTLR (GICD_OFFSET + 0x000)
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#define GICD_TYPER (GICD_OFFSET + 0x004)
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#define GICD_IIDR (GICD_OFFSET + 0x008)
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#define GICD_IGROUPR(n) (GICD_OFFSET + 0x080 + (n) * 4)
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#define GICD_ISENABLER(n) (GICD_OFFSET + 0x100 + (n) * 4)
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#define GICD_ICENABLER(n) (GICD_OFFSET + 0x180 + (n) * 4)
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#define GICD_ISPENDR(n) (GICD_OFFSET + 0x200 + (n) * 4)
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#define GICD_ICPENDR(n) (GICD_OFFSET + 0x280 + (n) * 4)
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#define GICD_ISACTIVER(n) (GICD_OFFSET + 0x300 + (n) * 4)
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#define GICD_ICACTIVER(n) (GICD_OFFSET + 0x380 + (n) * 4)
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#define GICD_IPRIORITYR(n) (GICD_OFFSET + 0x400 + (n) * 4)
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#define GICD_ITARGETSR(n) (GICD_OFFSET + 0x800 + (n) * 4)
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#define GICD_ICFGR(n) (GICD_OFFSET + 0xc00 + (n) * 4)
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#define GICD_NSACR(n) (GICD_OFFSET + 0xe00 + (n) * 4)
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#define GICD_SGIR (GICD_OFFSET + 0xf00)
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#define GICD_CPENDSGIR(n) (GICD_OFFSET + 0xf10 + (n) * 4)
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#define GICD_SPENDSGIR(n) (GICD_OFFSET + 0xf20 + (n) * 4)
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#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
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#define GIC_REG_COUNT(bit_per_reg) DIV_ROUND_UP(MAX_INT, (bit_per_reg))
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#define DEFINE_GIC_SHADOW_REG(name, bit_per_reg, init_val, init_from) \
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uint32_t (name)[GIC_REG_COUNT(bit_per_reg)] = { \
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[((init_from) / (bit_per_reg)) ... \
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(GIC_REG_COUNT(bit_per_reg) - 1)] = (init_val) \
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}
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#if WITH_LIB_SM
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static DEFINE_GIC_SHADOW_REG(gicd_igroupr, 32, ~0U, 0);
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#endif
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static DEFINE_GIC_SHADOW_REG(gicd_itargetsr, 4, 0x01010101, 32);
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// accessor routines for GIC registers that go through the mmio interface
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static inline uint32_t gicreg_read32(uint32_t gic, uint32_t register_offset) {
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return mmio_read32((volatile uint32_t *)(GICBASE(gic) + register_offset));
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}
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static inline void gicreg_write32(uint32_t gic, uint32_t register_offset, uint32_t value) {
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mmio_write32((volatile uint32_t *)(GICBASE(gic) + register_offset), value);
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}
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static void gic_set_enable(uint vector, bool enable) {
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uint reg = vector / 32;
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uint32_t mask = 1ULL << (vector % 32);
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if (enable) {
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gicreg_write32(0, GICD_ISENABLER(reg), mask);
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} else {
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gicreg_write32(0, GICD_ICENABLER(reg), mask);
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}
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}
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static void arm_gic_init_percpu(uint level) {
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#if WITH_LIB_SM
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gicreg_write32(0, GICC_CTLR, 0xb); // enable GIC0 and select fiq mode for secure
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gicreg_write32(0, GICD_IGROUPR(0), ~0U); /* GICD_IGROUPR0 is banked */
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#else
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gicreg_write32(0, GICC_CTLR, 1); // enable GIC0
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#endif
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gicreg_write32(0, GICC_PMR, 0xFF); // unmask interrupts at all priority levels
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}
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LK_INIT_HOOK_FLAGS(arm_gic_init_percpu,
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arm_gic_init_percpu,
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LK_INIT_LEVEL_PLATFORM_EARLY, LK_INIT_FLAG_SECONDARY_CPUS);
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static void arm_gic_suspend_cpu(uint level) {
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suspend_resume_fiq(false, false);
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}
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LK_INIT_HOOK_FLAGS(arm_gic_suspend_cpu, arm_gic_suspend_cpu,
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LK_INIT_LEVEL_PLATFORM, LK_INIT_FLAG_CPU_SUSPEND);
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static void arm_gic_resume_cpu(uint level) {
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spin_lock_saved_state_t state;
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bool resume_gicd = false;
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spin_lock_save(&gicd_lock, &state, GICD_LOCK_FLAGS);
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if (!(gicreg_read32(0, GICD_CTLR) & 1)) {
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dprintf(SPEW, "%s: distibutor is off, calling arm_gic_init instead\n", __func__);
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arm_gic_init();
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resume_gicd = true;
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} else {
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arm_gic_init_percpu(0);
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}
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spin_unlock_restore(&gicd_lock, state, GICD_LOCK_FLAGS);
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suspend_resume_fiq(true, resume_gicd);
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}
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LK_INIT_HOOK_FLAGS(arm_gic_resume_cpu, arm_gic_resume_cpu,
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LK_INIT_LEVEL_PLATFORM, LK_INIT_FLAG_CPU_RESUME);
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static uint arm_gic_max_cpu(void) {
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return (gicreg_read32(0, GICD_TYPER) >> 5) & 0x7;
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}
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static status_t gic_configure_interrupt(unsigned int vector,
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enum interrupt_trigger_mode tm,
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enum interrupt_polarity pol) {
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//Only configurable for SPI interrupts
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if ((vector >= MAX_INT) || (vector < GIC_BASE_SPI)) {
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return ERR_INVALID_ARGS;
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}
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if (pol != IRQ_POLARITY_ACTIVE_HIGH) {
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// TODO: polarity should actually be configure through a GPIO controller
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return ERR_NOT_SUPPORTED;
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}
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// type is encoded with two bits, MSB of the two determine type
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// 16 irqs encoded per ICFGR register
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uint32_t reg_ndx = vector >> 4;
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uint32_t bit_shift = ((vector & 0xf) << 1) + 1;
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uint32_t reg_val = gicreg_read32(0, GICD_ICFGR(reg_ndx));
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if (tm == IRQ_TRIGGER_MODE_EDGE) {
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reg_val |= (1U << bit_shift);
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} else {
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reg_val &= ~(1U << bit_shift);
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}
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gicreg_write32(0, GICD_ICFGR(reg_ndx), reg_val);
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return NO_ERROR;
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}
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void arm_gic_init(void) {
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// Are we a GICv2?
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// NOTE: probably crashes on a V3
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uint32_t iidr = gicreg_read32(0, GICC_IIDR);
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if (BITS_SHIFT(iidr, 19, 16) != 0x2) {
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dprintf(CRITICAL, "GIC: not a GICv2, IIDR 0x%x\n", iidr);
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return;
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}
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dprintf(INFO, "GIC: version %lu\n", BITS_SHIFT(iidr, 19, 16));
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// Read how many cpus and interrupts we support
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uint32_t type = gicreg_read32(0, GICD_TYPER);
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uint32_t cpu_count = (type >> 5) & 0x7;
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uint32_t it_lines = (type & 0x1f) + 1;
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if (it_lines > 6) {
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it_lines = 6;
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}
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int max_int = (int)it_lines * 32;
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if (max_int > MAX_INT) {
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max_int = MAX_INT;
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}
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dprintf(INFO, "GICv2: GICD_TYPER 0x%x, cpu_count %u, max_int %u\n", type, cpu_count + 1, max_int);
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for (int i = 0; i < max_int; i+= 32) {
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gicreg_write32(0, GICD_ICENABLER(i / 32), ~0);
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gicreg_write32(0, GICD_ICPENDR(i / 32), ~0);
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}
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if (arm_gic_max_cpu() > 0) {
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/* Set external interrupts to target cpu 0 */
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for (int i = 32; i < max_int; i += 4) {
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gicreg_write32(0, GICD_ITARGETSR(i / 4), gicd_itargetsr[i / 4]);
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}
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}
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// Initialize all the SPIs to edge triggered
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for (int i = 32; i < max_int; i++) {
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gic_configure_interrupt(i, IRQ_TRIGGER_MODE_EDGE, IRQ_POLARITY_ACTIVE_HIGH);
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}
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gicreg_write32(0, GICD_CTLR, 1); // enable GIC0
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#if WITH_LIB_SM
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gicreg_write32(0, GICD_CTLR, 3); // enable GIC0 ns interrupts
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/*
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* Iterate through all IRQs and set them to non-secure
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* mode. This will allow the non-secure side to handle
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* all the interrupts we don't explicitly claim.
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*/
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for (int i = 32; i < max_int; i += 32) {
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u_int reg = i / 32;
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gicreg_write32(0, GICD_IGROUPR(reg), gicd_igroupr[reg]);
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}
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#endif
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arm_gic_init_percpu(0);
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}
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static status_t arm_gic_set_secure_locked(u_int irq, bool secure) {
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#if WITH_LIB_SM
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int reg = irq / 32;
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uint32_t mask = 1ULL << (irq % 32);
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if (irq >= MAX_INT)
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return ERR_INVALID_ARGS;
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if (secure)
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gicreg_write32(0, GICD_IGROUPR(reg), (gicd_igroupr[reg] &= ~mask));
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else
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gicreg_write32(0, GICD_IGROUPR(reg), (gicd_igroupr[reg] |= mask));
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LTRACEF("irq %d, secure %d, GICD_IGROUP%d = %x\n",
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irq, secure, reg, gicreg_read32(0, GICD_IGROUPR(reg)));
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#endif
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return NO_ERROR;
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}
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static status_t arm_gic_set_target_locked(u_int irq, u_int cpu_mask, u_int enable_mask) {
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u_int reg = irq / 4;
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u_int shift = 8 * (irq % 4);
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u_int old_val;
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u_int new_val;
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cpu_mask = (cpu_mask & 0xff) << shift;
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enable_mask = (enable_mask << shift) & cpu_mask;
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old_val = gicreg_read32(0, GICD_ITARGETSR(reg));
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new_val = (gicd_itargetsr[reg] & ~cpu_mask) | enable_mask;
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gicreg_write32(0, GICD_ITARGETSR(reg), (gicd_itargetsr[reg] = new_val));
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LTRACEF("irq %i, GICD_ITARGETSR%d %x => %x (got %x)\n",
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irq, reg, old_val, new_val, gicreg_read32(0, GICD_ITARGETSR(reg)));
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return NO_ERROR;
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}
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static uint8_t arm_gic_get_priority(u_int irq) {
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u_int reg = irq / 4;
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u_int shift = 8 * (irq % 4);
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return (gicreg_read32(0, GICD_IPRIORITYR(reg)) >> shift) & 0xff;
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}
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static status_t arm_gic_set_priority_locked(u_int irq, uint8_t priority) {
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u_int reg = irq / 4;
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u_int shift = 8 * (irq % 4);
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u_int mask = 0xff << shift;
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uint32_t regval;
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regval = gicreg_read32(0, GICD_IPRIORITYR(reg));
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LTRACEF("irq %i, old GICD_IPRIORITYR%d = %x\n", irq, reg, regval);
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regval = (regval & ~mask) | ((uint32_t)priority << shift);
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gicreg_write32(0, GICD_IPRIORITYR(reg), regval);
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LTRACEF("irq %i, new GICD_IPRIORITYR%d = %x, req %x\n",
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irq, reg, gicreg_read32(0, GICD_IPRIORITYR(reg)), regval);
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return 0;
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}
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status_t arm_gic_sgi(u_int irq, u_int flags, u_int cpu_mask) {
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u_int val =
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((flags & ARM_GIC_SGI_FLAG_TARGET_FILTER_MASK) << 24) |
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((cpu_mask & 0xff) << 16) |
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((flags & ARM_GIC_SGI_FLAG_NS) ? (1U << 15) : 0) |
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(irq & 0xf);
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if (irq >= 16)
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return ERR_INVALID_ARGS;
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LTRACEF("GICD_SGIR: %x\n", val);
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gicreg_write32(0, GICD_SGIR, val);
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return NO_ERROR;
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}
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status_t mask_interrupt(unsigned int vector) {
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if (vector >= MAX_INT)
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return ERR_INVALID_ARGS;
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if (arm_gic_interrupt_change_allowed(vector))
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gic_set_enable(vector, false);
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return NO_ERROR;
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}
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status_t unmask_interrupt(unsigned int vector) {
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if (vector >= MAX_INT)
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return ERR_INVALID_ARGS;
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if (arm_gic_interrupt_change_allowed(vector))
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gic_set_enable(vector, true);
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return NO_ERROR;
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}
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static
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enum handler_return __platform_irq(struct iframe *frame) {
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// get the current vector
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uint32_t iar = gicreg_read32(0, GICC_IAR);
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unsigned int vector = iar & 0x3ff;
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if (vector >= 0x3fe) {
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// spurious
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return INT_NO_RESCHEDULE;
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}
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THREAD_STATS_INC(interrupts);
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KEVLOG_IRQ_ENTER(vector);
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uint cpu = arch_curr_cpu_num();
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LTRACEF_LEVEL(2, "iar 0x%x cpu %u currthread %p vector %d pc 0x%lx\n", iar, cpu,
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get_current_thread(), vector, (uintptr_t)IFRAME_PC(frame));
|
|
|
|
// deliver the interrupt
|
|
enum handler_return ret;
|
|
|
|
ret = INT_NO_RESCHEDULE;
|
|
struct int_handler_struct *handler = get_int_handler(vector, cpu);
|
|
if (handler->handler)
|
|
ret = handler->handler(handler->arg);
|
|
|
|
gicreg_write32(0, GICC_EOIR, iar);
|
|
|
|
LTRACEF_LEVEL(2, "cpu %u exit %d\n", cpu, ret);
|
|
|
|
KEVLOG_IRQ_EXIT(vector);
|
|
|
|
return ret;
|
|
}
|
|
|
|
enum handler_return platform_irq(struct iframe *frame);
|
|
enum handler_return platform_irq(struct iframe *frame) {
|
|
#if WITH_LIB_SM
|
|
uint32_t ahppir = gicreg_read32(0, GICC_AHPPIR);
|
|
uint32_t pending_irq = ahppir & 0x3ff;
|
|
struct int_handler_struct *h;
|
|
uint cpu = arch_curr_cpu_num();
|
|
|
|
LTRACEF("ahppir %d\n", ahppir);
|
|
if (pending_irq < MAX_INT && get_int_handler(pending_irq, cpu)->handler) {
|
|
enum handler_return ret = 0;
|
|
uint32_t irq;
|
|
uint8_t old_priority;
|
|
spin_lock_saved_state_t state;
|
|
|
|
spin_lock_save(&gicd_lock, &state, GICD_LOCK_FLAGS);
|
|
|
|
/* Temporarily raise the priority of the interrupt we want to
|
|
* handle so another interrupt does not take its place before
|
|
* we can acknowledge it.
|
|
*/
|
|
old_priority = arm_gic_get_priority(pending_irq);
|
|
arm_gic_set_priority_locked(pending_irq, 0);
|
|
DSB;
|
|
irq = gicreg_read32(0, GICC_AIAR) & 0x3ff;
|
|
arm_gic_set_priority_locked(pending_irq, old_priority);
|
|
|
|
spin_unlock_restore(&gicd_lock, state, GICD_LOCK_FLAGS);
|
|
|
|
LTRACEF("irq %d\n", irq);
|
|
if (irq < MAX_INT && (h = get_int_handler(pending_irq, cpu))->handler)
|
|
ret = h->handler(h->arg);
|
|
else
|
|
TRACEF("unexpected irq %d != %d may get lost\n", irq, pending_irq);
|
|
gicreg_write32(0, GICC_AEOIR, irq);
|
|
return ret;
|
|
}
|
|
return sm_handle_irq();
|
|
#else
|
|
return __platform_irq(frame);
|
|
#endif
|
|
}
|
|
|
|
void platform_fiq(struct iframe *frame);
|
|
void platform_fiq(struct iframe *frame) {
|
|
#if WITH_LIB_SM
|
|
sm_handle_fiq();
|
|
#else
|
|
PANIC_UNIMPLEMENTED;
|
|
#endif
|
|
}
|
|
|
|
#if WITH_LIB_SM
|
|
static status_t arm_gic_get_next_irq_locked(u_int min_irq, bool per_cpu) {
|
|
u_int irq;
|
|
u_int max_irq = per_cpu ? GIC_MAX_PER_CPU_INT : MAX_INT;
|
|
uint cpu = arch_curr_cpu_num();
|
|
|
|
if (!per_cpu && min_irq < GIC_MAX_PER_CPU_INT)
|
|
min_irq = GIC_MAX_PER_CPU_INT;
|
|
|
|
for (irq = min_irq; irq < max_irq; irq++)
|
|
if (get_int_handler(irq, cpu)->handler)
|
|
return irq;
|
|
|
|
return SM_ERR_END_OF_INPUT;
|
|
}
|
|
|
|
long smc_intc_get_next_irq(smc32_args_t *args) {
|
|
status_t ret;
|
|
spin_lock_saved_state_t state;
|
|
|
|
spin_lock_save(&gicd_lock, &state, GICD_LOCK_FLAGS);
|
|
|
|
arm_gic_non_secure_interrupts_frozen = true;
|
|
ret = arm_gic_get_next_irq_locked(args->params[0], args->params[1]);
|
|
LTRACEF("min_irq %d, per_cpu %d, ret %d\n",
|
|
args->params[0], args->params[1], ret);
|
|
|
|
spin_unlock_restore(&gicd_lock, state, GICD_LOCK_FLAGS);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static u_long enabled_fiq_mask[BITMAP_NUM_WORDS(MAX_INT)];
|
|
|
|
static void bitmap_update_locked(u_long *bitmap, u_int bit, bool set) {
|
|
u_long mask = 1UL << BITMAP_BIT_IN_WORD(bit);
|
|
|
|
bitmap += BITMAP_WORD(bit);
|
|
if (set)
|
|
*bitmap |= mask;
|
|
else
|
|
*bitmap &= ~mask;
|
|
}
|
|
|
|
long smc_intc_request_fiq(smc32_args_t *args) {
|
|
u_int fiq = args->params[0];
|
|
bool enable = args->params[1];
|
|
spin_lock_saved_state_t state;
|
|
|
|
dprintf(SPEW, "%s: fiq %d, enable %d\n", __func__, fiq, enable);
|
|
spin_lock_save(&gicd_lock, &state, GICD_LOCK_FLAGS);
|
|
|
|
arm_gic_set_secure_locked(fiq, true);
|
|
arm_gic_set_target_locked(fiq, ~0, ~0);
|
|
arm_gic_set_priority_locked(fiq, 0);
|
|
|
|
gic_set_enable(fiq, enable);
|
|
bitmap_update_locked(enabled_fiq_mask, fiq, enable);
|
|
|
|
dprintf(SPEW, "%s: fiq %d, enable %d done\n", __func__, fiq, enable);
|
|
|
|
spin_unlock_restore(&gicd_lock, state, GICD_LOCK_FLAGS);
|
|
|
|
return NO_ERROR;
|
|
}
|
|
|
|
static u_int current_fiq[8] = { 0x3ff, 0x3ff, 0x3ff, 0x3ff, 0x3ff, 0x3ff, 0x3ff, 0x3ff };
|
|
|
|
static bool update_fiq_targets(u_int cpu, bool enable, u_int triggered_fiq, bool resume_gicd) {
|
|
u_int i, j;
|
|
u_long mask;
|
|
u_int fiq;
|
|
bool smp = arm_gic_max_cpu() > 0;
|
|
bool ret = false;
|
|
|
|
spin_lock(&gicd_lock); /* IRQs and FIQs are already masked */
|
|
for (i = 0; i < BITMAP_NUM_WORDS(MAX_INT); i++) {
|
|
mask = enabled_fiq_mask[i];
|
|
while (mask) {
|
|
j = _ffz(~mask);
|
|
mask &= ~(1UL << j);
|
|
fiq = i * BITMAP_BITS_PER_WORD + j;
|
|
if (fiq == triggered_fiq)
|
|
ret = true;
|
|
LTRACEF("cpu %d, irq %i, enable %d\n", cpu, fiq, enable);
|
|
if (smp)
|
|
arm_gic_set_target_locked(fiq, 1U << cpu, enable ? ~0 : 0);
|
|
if (!smp || resume_gicd)
|
|
gic_set_enable(fiq, enable);
|
|
}
|
|
}
|
|
spin_unlock(&gicd_lock);
|
|
return ret;
|
|
}
|
|
|
|
static void suspend_resume_fiq(bool resume_gicc, bool resume_gicd) {
|
|
u_int cpu = arch_curr_cpu_num();
|
|
|
|
ASSERT(cpu < 8);
|
|
|
|
update_fiq_targets(cpu, resume_gicc, ~0, resume_gicd);
|
|
}
|
|
|
|
status_t sm_intc_fiq_enter(void) {
|
|
u_int cpu = arch_curr_cpu_num();
|
|
u_int irq = gicreg_read32(0, GICC_IAR) & 0x3ff;
|
|
bool fiq_enabled;
|
|
|
|
ASSERT(cpu < 8);
|
|
|
|
LTRACEF("cpu %d, irq %i\n", cpu, irq);
|
|
|
|
if (irq >= 1020) {
|
|
LTRACEF("spurious fiq: cpu %d, old %d, new %d\n", cpu, current_fiq[cpu], irq);
|
|
return ERR_NO_MSG;
|
|
}
|
|
|
|
fiq_enabled = update_fiq_targets(cpu, false, irq, false);
|
|
gicreg_write32(0, GICC_EOIR, irq);
|
|
|
|
if (current_fiq[cpu] != 0x3ff) {
|
|
dprintf(INFO, "more than one fiq active: cpu %d, old %d, new %d\n", cpu, current_fiq[cpu], irq);
|
|
return ERR_ALREADY_STARTED;
|
|
}
|
|
|
|
if (!fiq_enabled) {
|
|
dprintf(INFO, "got disabled fiq: cpu %d, new %d\n", cpu, irq);
|
|
return ERR_NOT_READY;
|
|
}
|
|
|
|
current_fiq[cpu] = irq;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void sm_intc_fiq_exit(void) {
|
|
u_int cpu = arch_curr_cpu_num();
|
|
|
|
ASSERT(cpu < 8);
|
|
|
|
LTRACEF("cpu %d, irq %i\n", cpu, current_fiq[cpu]);
|
|
if (current_fiq[cpu] == 0x3ff) {
|
|
dprintf(INFO, "%s: no fiq active, cpu %d\n", __func__, cpu);
|
|
return;
|
|
}
|
|
update_fiq_targets(cpu, true, current_fiq[cpu], false);
|
|
current_fiq[cpu] = 0x3ff;
|
|
}
|
|
#endif
|