664bb17afa
- X86 cpuid feature list dump was using the wrong array and walking off the end of one. - GICv2 code had a left shift by up to 31 of an integer. Needs to be unsigned. - PLIC same as GIC code. - fdtwalker code should be using a bytewise accessor based helper function for reading large integers out of an unaliged FDT. - PCI BIOS32 search code could do a 32bit unaligned read of a string, switch to using memcmp.
291 lines
10 KiB
C
291 lines
10 KiB
C
/*
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* Copyright (c) 2019 Travis Geiselbrecht
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* Copyright 2016 The Fuchsia Authors
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files
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* (the "Software"), to deal in the Software without restriction,
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* including without limitation the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <arch/x86/feature.h>
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#include <lk/bits.h>
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#include <lk/debug.h>
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#include <lk/trace.h>
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#include <arch/x86.h>
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#include <assert.h>
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#include <string.h>
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#define LOCAL_TRACE 0
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enum x86_cpu_vendor __x86_cpu_vendor = X86_CPU_VENDOR_INTEL;
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enum x86_cpu_level __x86_cpu_level = X86_CPU_LEVEL_386; // start off assuming 386
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struct x86_model_info __x86_model;
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bool has_cpuid = false;
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/* a saved cache of three banks of cpuids loaded a boot */
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struct x86_cpuid_leaf saved_cpuids[__X86_MAX_SUPPORTED_CPUID + 1];
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struct x86_cpuid_leaf saved_cpuids_hyp[__X86_MAX_SUPPORTED_CPUID_HYP - X86_CPUID_HYP_BASE + 1];
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struct x86_cpuid_leaf saved_cpuids_ext[__X86_MAX_SUPPORTED_CPUID_EXT - X86_CPUID_EXT_BASE + 1];
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uint32_t max_cpuid_leaf = 0;
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uint32_t max_cpuid_leaf_hyp = 0;
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uint32_t max_cpuid_leaf_ext = 0;
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static enum x86_cpu_vendor match_cpu_vendor_string(const char *str) {
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// from table at https://www.sandpile.org/x86/cpuid.htm#level_0000_0000h
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if (!strcmp(str, "GenuineIntel")) {
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return X86_CPU_VENDOR_INTEL;
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}
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if (!strcmp(str, "UMC UMC UMC ")) {
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return X86_CPU_VENDOR_UMC;
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}
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if (!strcmp(str, "AuthenticAMD")) {
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return X86_CPU_VENDOR_AMD;
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}
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if (!strcmp(str, "CyrixInstead")) {
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return X86_CPU_VENDOR_CYRIX;
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}
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if (!strcmp(str, "NexGenDriven")) {
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return X86_CPU_VENDOR_NEXGEN;
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}
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if (!strcmp(str, "CentaurHauls")) {
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return X86_CPU_VENDOR_CENTAUR;
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}
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if (!strcmp(str, "RiseRiseRise")) {
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return X86_CPU_VENDOR_RISE;
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}
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if (!strcmp(str, "SiS SiS SiS ")) {
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return X86_CPU_VENDOR_SIS;
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}
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if (!strcmp(str, "GenuineTMx86")) {
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return X86_CPU_VENDOR_TRANSMETA;
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}
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if (!strcmp(str, "Geode by NSC")) {
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return X86_CPU_VENDOR_NSC;
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}
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return X86_CPU_VENDOR_UNKNOWN;
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}
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static void x86_cpu_detect(void) {
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if (X86_LEGACY) {
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// inspired by http://www.rcollins.org/ddj/Sep96/Sep96.html
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// try to detect a 486
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// set the EFLAGS.AC bit, see if it sets
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uint32_t flags = x86_save_flags();
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x86_restore_flags(flags | X86_FLAGS_AC);
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if (x86_save_flags() & X86_FLAGS_AC) {
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__x86_cpu_level = X86_CPU_LEVEL_486;
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// test EFLAGS.ID flag
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x86_restore_flags(flags | X86_FLAGS_ID);
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if (x86_save_flags() & X86_FLAGS_ID) {
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has_cpuid = true;
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}
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}
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} else {
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// at least a pentium and has cpuid
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__x86_cpu_level = X86_CPU_LEVEL_PENTIUM;
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has_cpuid = true;
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}
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if (has_cpuid) {
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uint32_t a, b, c, d;
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// read the max basic cpuid leaf
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cpuid(X86_CPUID_BASE, &a, &b, &c, &d);
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max_cpuid_leaf = MIN(a, __X86_MAX_SUPPORTED_CPUID);;
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LTRACEF("cpuid leaf 0: %#x %#x %#x %#x\n", a, b, c, d);
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// read the vendor string
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union {
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uint32_t reg[3];
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char str[13];
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} vs;
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vs.reg[0] = b;
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vs.reg[1] = d;
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vs.reg[2] = c;
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vs.str[12] = 0;
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__x86_cpu_vendor = match_cpu_vendor_string(vs.str);
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LTRACEF("vendor string '%s' from cpuid\n", vs.str);
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// read max extended cpuid leaf
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cpuid(X86_CPUID_EXT_BASE, &a, &b, &c, &d);
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if (a >= X86_CPUID_EXT_BASE) {
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max_cpuid_leaf_ext = MIN(a, __X86_MAX_SUPPORTED_CPUID_EXT);
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}
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// read max hypervisor leaf
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cpuid(X86_CPUID_HYP_BASE, &a, &b, &c, &d);
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// Check that it's an understood hypervisor leaf
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if ((b == 0x4b4d564b && c == 0x564b4d56 && d == 0x4d) || /* KVMKVMKVM */
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(b == 0x54474354 && c == 0x43544743 && d == 0x47435447)) { /* TCGTCGTCGTCG */
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max_cpuid_leaf_hyp = MIN(a, __X86_MAX_SUPPORTED_CPUID_HYP);
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} else {
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max_cpuid_leaf_hyp = 0;
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}
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} else {
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__x86_cpu_vendor = X86_CPU_VENDOR_INTEL; // intrinsically Intel without cpuid
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}
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// detect and populate the x86_model structure
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if (has_cpuid && max_cpuid_leaf >= 1) {
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uint32_t a, b, c, d;
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cpuid(X86_CPUID_MODEL_FEATURES, &a, &b, &c, &d);
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LTRACEF("cpuid leaf 1: %#x %#x %#x %#x\n", a, b, c, d);
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__x86_model.processor_type = BITS_SHIFT(a, 13, 12);
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__x86_model.family = BITS_SHIFT(a, 11, 8);
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__x86_model.model = BITS_SHIFT(a, 7, 4);
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__x86_model.stepping = BITS_SHIFT(a, 3, 0);
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__x86_model.display_family = __x86_model.family;
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__x86_model.display_model = __x86_model.model;
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uint32_t ext_family = BITS_SHIFT(a, 27, 20);
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uint32_t ext_model = BITS_SHIFT(a, 19, 16);
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switch (__x86_model.family) {
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case 4:
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__x86_cpu_level = X86_CPU_LEVEL_486;
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break;
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case 5:
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__x86_cpu_level = X86_CPU_LEVEL_PENTIUM;
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break;
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case 6:
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__x86_cpu_level = X86_CPU_LEVEL_PENTIUM_PRO;
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if (x86_get_cpu_vendor() == X86_CPU_VENDOR_INTEL) {
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__x86_model.display_model |= ext_model << 4; // extended model field extends the regular model
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}
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break;
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case 0xf:
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__x86_cpu_level = X86_CPU_LEVEL_PENTIUM_PRO;
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__x86_model.display_family += ext_family; // family 0xf stuff is extended by bits 27:20
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__x86_model.display_model |= ext_model << 4; // extended model field extends the regular model
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break;
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default:
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// unhandled decode, assume ppro+ level
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__x86_cpu_level = X86_CPU_LEVEL_PENTIUM_PRO;
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break;
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}
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}
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}
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/* early detection of cpu features on cpu 0, before the kernel is scheduling */
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void x86_feature_early_init(void) {
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x86_cpu_detect();
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// cache a copy of the cpuid bits
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if (has_cpuid) {
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for (uint32_t i = 0; i <= max_cpuid_leaf; i++) {
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cpuid_c(i, 0, &saved_cpuids[i].a, &saved_cpuids[i].b, &saved_cpuids[i].c, &saved_cpuids[i].d);
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}
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if (max_cpuid_leaf_ext > 0) {
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for (uint32_t i = X86_CPUID_EXT_BASE; i <= max_cpuid_leaf_ext; i++) {
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uint32_t index = i - X86_CPUID_EXT_BASE;
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cpuid_c(i, 0, &saved_cpuids_ext[index].a, &saved_cpuids_ext[index].b, &saved_cpuids_ext[index].c,
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&saved_cpuids_ext[index].d);
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}
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}
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if (max_cpuid_leaf_hyp > 0) {
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for (uint32_t i = X86_CPUID_HYP_BASE; i <= max_cpuid_leaf_hyp; i++) {
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uint32_t index = i - X86_CPUID_HYP_BASE;
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cpuid_c(i, 0, &saved_cpuids_hyp[index].a, &saved_cpuids_hyp[index].b, &saved_cpuids_hyp[index].c,
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&saved_cpuids_hyp[index].d);
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}
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}
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}
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}
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static void x86_feature_dump_cpuid(void) {
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for (uint32_t i = X86_CPUID_BASE; i <= max_cpuid_leaf; i++) {
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printf("X86: cpuid leaf %#x: %08x %08x %08x %08x\n", i,
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saved_cpuids[i - X86_CPUID_BASE].a, saved_cpuids[i - X86_CPUID_BASE].b, saved_cpuids[i - X86_CPUID_BASE].c, saved_cpuids[i - X86_CPUID_BASE].d);
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}
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for (uint32_t i = X86_CPUID_HYP_BASE; i <= max_cpuid_leaf_hyp; i++) {
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uint32_t index = i - X86_CPUID_HYP_BASE;
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printf("X86: cpuid leaf %#x: %08x %08x %08x %08x\n", i,
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saved_cpuids_hyp[index].a, saved_cpuids_hyp[index].b, saved_cpuids_hyp[index].c, saved_cpuids_hyp[index].d);
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}
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for (uint32_t i = X86_CPUID_EXT_BASE; i <= max_cpuid_leaf_ext; i++) {
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uint32_t index = i - X86_CPUID_EXT_BASE;
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printf("X86: cpuid leaf %#x: %08x %08x %08x %08x\n", i,
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saved_cpuids_ext[index].a, saved_cpuids_ext[index].b, saved_cpuids_ext[index].c, saved_cpuids_ext[index].d);
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}
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}
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/* later feature init hook, called after the kernel is able to schedule */
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void x86_feature_init(void) {
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dprintf(SPEW, "X86: detected cpu level %d has_cpuid %d\n", x86_get_cpu_level(), has_cpuid);
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if (has_cpuid) {
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dprintf(SPEW, "X86: max cpuid leaf %#x ext %#x hyp %#x\n",
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max_cpuid_leaf, max_cpuid_leaf_ext, max_cpuid_leaf_hyp);
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}
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if (has_cpuid) {
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// read the max basic cpuid leaf
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uint32_t a, b, c, d;
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cpuid(X86_CPUID_BASE, &a, &b, &c, &d);
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// read the vendor string
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union {
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uint32_t reg[3];
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char str[13];
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} vs;
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vs.reg[0] = b;
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vs.reg[1] = d;
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vs.reg[2] = c;
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vs.str[12] = 0;
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dprintf(SPEW, "X86: vendor string '%s'\n", vs.str);
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}
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const struct x86_model_info* model = x86_get_model();
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printf("X86: processor model info type %#x family %#x model %#x stepping %#x\n",
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model->processor_type, model->family, model->model, model->stepping);
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printf("\tdisplay_family %#x display_model %#x\n", model->display_family, model->display_model);
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if (has_cpuid && LK_DEBUGLEVEL > 1) {
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x86_feature_dump_cpuid();
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}
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}
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bool x86_get_cpuid_subleaf(enum x86_cpuid_leaf_num num, uint32_t subleaf, struct x86_cpuid_leaf* leaf) {
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// make sure the leaf number is within the detected range of the three blocks we know about
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if (num < X86_CPUID_HYP_BASE) {
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if (num > max_cpuid_leaf) {
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return false;
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}
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} else if (num < X86_CPUID_EXT_BASE) {
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if (num > max_cpuid_leaf_hyp) {
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return false;
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}
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} else if (num > max_cpuid_leaf_ext) {
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return false;
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}
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cpuid_c((uint32_t)num, subleaf, &leaf->a, &leaf->b, &leaf->c, &leaf->d);
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return true;
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}
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