c3ea652c1f
The IRQ calculation for the virtio range was off by 8, which caused the virtio code to override the interrupt registration for the RTC, which caused it to stop firing. Clean up the #defines that define irq mappings to fix this issue.
132 lines
3.3 KiB
C
132 lines
3.3 KiB
C
/*
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* Copyright (c) 2021 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include "platform_p.h"
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#include <assert.h>
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#include <lk/bits.h>
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#include <lk/err.h>
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#include <lk/debug.h>
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#include <lk/reg.h>
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#include <lk/trace.h>
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#include <kernel/debug.h>
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#include <kernel/thread.h>
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#include <platform/interrupts.h>
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#include <platform/virt.h>
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#define LOCAL_TRACE 0
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// implementation of PIC at
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// https://github.com/qemu/qemu/blob/master/hw/intc/goldfish_pic.c
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enum {
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REG_STATUS = 0x00,
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REG_IRQ_PENDING = 0x04,
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REG_IRQ_DISABLE_ALL = 0x08,
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REG_DISABLE = 0x0c,
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REG_ENABLE = 0x10,
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};
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volatile uint32_t * const goldfish_pic_base = (void *)VIRT_GF_PIC_MMIO_BASE;
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static struct int_handlers {
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int_handler handler;
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void *arg;
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} handlers[NUM_IRQS];
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static void write_reg(unsigned int pic, unsigned int reg, uint32_t val) {
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goldfish_pic_base[(0x1000 * pic + reg) / 4] = val;
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}
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static uint32_t read_reg(unsigned int pic, unsigned int reg) {
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return goldfish_pic_base[(0x1000 * pic + reg) / 4];
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}
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static void dump_pic(unsigned int i) {
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dprintf(INFO, "PIC %d: status %u pending %#x\n", i, read_reg(i, REG_STATUS), read_reg(i, REG_IRQ_PENDING));
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}
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static void dump_all_pics(void) {
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for (int i = 0; i < VIRT_GF_PIC_NB; i++) {
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dump_pic(i);
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}
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}
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static unsigned int irq_to_pic_num(unsigned int vector) {
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return vector / 32;
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}
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static unsigned int irq_to_pic_vec(unsigned int vector) {
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return vector % 32;
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}
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void pic_early_init(void) {
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}
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void pic_init(void) {
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dump_all_pics();
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}
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status_t mask_interrupt(unsigned int vector) {
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LTRACEF("vector %u\n", vector);
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write_reg(irq_to_pic_num(vector), REG_DISABLE, 1U << irq_to_pic_vec(vector));
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return NO_ERROR;
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}
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status_t unmask_interrupt(unsigned int vector) {
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LTRACEF("vector %u\n", vector);
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write_reg(irq_to_pic_num(vector), REG_ENABLE, 1U << irq_to_pic_vec(vector));
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return NO_ERROR;
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}
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void register_int_handler(unsigned int vector, int_handler handler, void *arg) {
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LTRACEF("vector %u handler %p arg %p\n", vector, handler, arg);
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DEBUG_ASSERT(vector < NUM_IRQS);
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handlers[vector].handler = handler;
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handlers[vector].arg = arg;
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}
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enum handler_return m68k_platform_irq(uint8_t m68k_irq) {
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LTRACEF("m68k irq vector %d\n", m68k_irq);
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// translate m68k irqs to pic numbers
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// incoming IRQs are from 0x19-0x1f (autovectored 1 - 7 on the cpu)
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int pic_num;
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if (likely(m68k_irq >= 0x19 && m68k_irq <= 0x1f)) {
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pic_num = m68k_irq - 0x19;
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} else {
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panic("unhandled irq %d from cpu\n", m68k_irq);
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}
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// see what is pending
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uint32_t pending = read_reg(pic_num, REG_IRQ_PENDING);
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if (pending == 0) {
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// spurious
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return INT_NO_RESCHEDULE;
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}
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// find the lowest numbered bit set
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uint vector = ctz(pending) + pic_num * 32;
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LTRACEF("pic %d pending %#x vector %u\n", pic_num, pending, vector);
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THREAD_STATS_INC(interrupts);
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KEVLOG_IRQ_ENTER(vector);
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enum handler_return ret = INT_NO_RESCHEDULE;
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if (handlers[vector].handler) {
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ret = handlers[vector].handler(handlers[vector].arg);
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}
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// no need to ack the interrupt controller since all irqs are implicitly level
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KEVLOG_IRQ_EXIT(vector);
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return ret;
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}
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