63be190d8b
-added support for bringing up the clocks and setting up the gpio bits before starting the uart. -add a proper target init routine -add scripts to flash board via openocd -fixed bug in riscv interrupt save state where it wasn't saving mstatus on irq entry. -comment out cycle enabling, not implemented on this core
73 lines
2.9 KiB
C
73 lines
2.9 KiB
C
/*
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* Copyright (c) 2015 Travis Geiselbrecht
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files
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* (the "Software"), to deal in the Software without restriction,
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* including without limitation the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <assert.h>
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#include <trace.h>
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#include <debug.h>
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#include <stdint.h>
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#include <arch/riscv.h>
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#include <arch/ops.h>
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#define LOCAL_TRACE 0
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void arch_early_init(void) {
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// set the top level exception handler
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riscv_csr_write(mtvec, (uintptr_t)&riscv_exception_entry);
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// mask all exceptions, just in case
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riscv_csr_clear(mstatus, RISCV_STATUS_MIE);
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riscv_csr_clear(mie, RISCV_MIE_MTIE | RISCV_MIE_MSIE | RISCV_MIE_SEIE | RISCV_MIE_MEIE);
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// enable cycle counter (disabled for now, unimplemented on sifive-e)
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//riscv_csr_set(mcounteren, 1);
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}
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void arch_init(void) {
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// print some arch info
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dprintf(INFO, "RISCV: mvendorid %#lx marchid %#lx mimpid %#lx mhartid %#lx\n",
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riscv_csr_read(mvendorid), riscv_csr_read(marchid),
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riscv_csr_read(mimpid), riscv_csr_read(mhartid));
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dprintf(INFO, "RISCV: misa %#lx\n", riscv_csr_read(misa));
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// enable external interrupts
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riscv_csr_set(mie, RISCV_MIE_MEIE);
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}
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void arch_idle(void) {
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// disabled for now, QEMU seems to have some trouble emulating wfi properly
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// also have trouble breaking into sifive-e board with openocd when wfi
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// __asm__ volatile("wfi");
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}
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void arch_chain_load(void *entry, ulong arg0, ulong arg1, ulong arg2, ulong arg3) {
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PANIC_UNIMPLEMENTED;
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}
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/* unimplemented cache operations */
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void arch_disable_cache(uint flags) { PANIC_UNIMPLEMENTED; }
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void arch_enable_cache(uint flags) { PANIC_UNIMPLEMENTED; }
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void arch_clean_cache_range(addr_t start, size_t len) { PANIC_UNIMPLEMENTED; }
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void arch_clean_invalidate_cache_range(addr_t start, size_t len) { PANIC_UNIMPLEMENTED; }
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void arch_invalidate_cache_range(addr_t start, size_t len) { PANIC_UNIMPLEMENTED; }
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void arch_sync_cache_range(addr_t start, size_t len) { PANIC_UNIMPLEMENTED; }
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