-Move the local apic driver to arch/x86 -Add routines to send IPIs between cpus Something is unstable at the moment and the system crashes after a while with random corruptions when using SMP.
319 lines
8.8 KiB
C
319 lines
8.8 KiB
C
/*
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* Copyright (c) 2009 Corey Tabaka
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include <sys/types.h>
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#include <lk/err.h>
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#include <lk/reg.h>
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#include <lk/debug.h>
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#include <lk/trace.h>
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#include <assert.h>
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#include <kernel/thread.h>
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#include <kernel/spinlock.h>
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#include <platform.h>
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#include <platform/interrupts.h>
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#include <platform/console.h>
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#include <platform/timer.h>
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#include <platform/pc.h>
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#include <platform/pc/timer.h>
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#include "platform_p.h"
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#include <arch/x86.h>
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#include <inttypes.h>
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#define LOCAL_TRACE 0
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// TODO: switch this logic to lib/fixed_point math
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static platform_timer_callback t_callback;
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static void *callback_arg;
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static spin_lock_t lock = SPIN_LOCK_INITIAL_VALUE;
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static uint64_t ticks_per_ms;
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// next callback event time in 32.32 fixed point milliseconds
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static uint64_t next_trigger_time;
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// if periodic, the delta to set to the next event. if oneshot, 0
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static uint64_t next_trigger_delta;
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// time in 32.32 fixed point milliseconds
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static volatile uint64_t timer_current_time;
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// delta time per periodic tick in 32.32
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static uint64_t timer_delta_time;
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#define INTERNAL_FREQ 1193182ULL
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#define INTERNAL_FREQ_3X 3579546ULL
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#define INTERNAL_FREQ_TICKS_PER_MS (INTERNAL_FREQ / 1000u)
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/* Maximum amount of time that can be program on the timer to schedule the next
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* interrupt, in milliseconds */
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#define MAX_TIMER_INTERVAL 55
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lk_time_t pit_current_time(void) {
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spin_lock_saved_state_t state;
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spin_lock_irqsave(&lock, state);
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lk_time_t time = (lk_time_t) (timer_current_time >> 32);
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spin_unlock_irqrestore(&lock, state);
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return time;
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}
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lk_bigtime_t pit_current_time_hires(void) {
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spin_lock_saved_state_t state;
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spin_lock_irqsave(&lock, state);
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lk_bigtime_t time = (lk_bigtime_t) ((timer_current_time >> 22) * 1000) >> 10;
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spin_unlock_irqrestore(&lock, state);
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return time;
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}
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static enum handler_return pit_timer_tick(void *arg) {
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if (next_trigger_time != 0 || next_trigger_delta) {
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LTRACEF("ntt %#" PRIx64 ", ntd %#" PRIx64 "\n", next_trigger_time, next_trigger_delta);
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}
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spin_lock(&lock);
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timer_current_time += timer_delta_time;
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spin_unlock(&lock);
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lk_time_t time = current_time();
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if (t_callback && next_trigger_time != 0 && timer_current_time >= next_trigger_time) {
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if (next_trigger_delta != 0) {
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uint64_t delta = timer_current_time - next_trigger_time;
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next_trigger_time = timer_current_time + next_trigger_delta - delta;
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} else {
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next_trigger_time = 0;
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}
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return t_callback(callback_arg, time);
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} else {
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return INT_NO_RESCHEDULE;
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}
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}
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static void set_pit_frequency(uint32_t frequency) {
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uint32_t count, remainder;
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LTRACEF("frequency %u\n", frequency);
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/* figure out the correct divisor for the desired frequency */
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if (frequency <= 18) {
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count = 0xffff;
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} else if (frequency >= INTERNAL_FREQ) {
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count = 1;
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} else {
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count = INTERNAL_FREQ_3X / frequency;
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remainder = INTERNAL_FREQ_3X % frequency;
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if (remainder >= INTERNAL_FREQ_3X / 2) {
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count += 1;
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}
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count /= 3;
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remainder = count % 3;
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if (remainder >= 1) {
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count += 1;
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}
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}
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uint16_t divisor = count & 0xffff;
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/*
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* funky math that i don't feel like explaining. essentially 32.32 fixed
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* point representation of the configured timer delta.
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*/
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timer_delta_time = (3685982306ULL * count) >> 10;
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LTRACEF("dt %#x.%08x\n", (uint32_t)(timer_delta_time >> 32), (uint32_t)(timer_delta_time & 0xffffffff));
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LTRACEF("divisor %" PRIu16 "\n", divisor);
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/*
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* setup the Programmable Interval Timer
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* timer 0, mode 2, binary counter, LSB followed by MSB
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*/
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outp(I8253_CONTROL_REG, 0x34);
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outp(I8253_DATA_REG, divisor & 0xff); // LSB
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outp(I8253_DATA_REG, divisor >> 8); // MSB
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}
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void pit_init(void) {
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// start the PIT at 1Khz in free-running mode to keep a time base
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timer_current_time = 0;
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ticks_per_ms = INTERNAL_FREQ/1000;
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set_pit_frequency(1000); // ~1ms granularity
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register_int_handler(INT_PIT, &pit_timer_tick, NULL);
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unmask_interrupt(INT_PIT);
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}
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status_t pit_set_periodic_timer(platform_timer_callback callback, void *arg, lk_time_t interval) {
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LTRACEF("pit_set_periodic_timer: interval %u\n", interval);
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spin_lock_saved_state_t state;
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spin_lock_irqsave(&lock, state);
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t_callback = callback;
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callback_arg = arg;
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next_trigger_delta = (uint64_t) interval << 32;
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next_trigger_time = timer_current_time + next_trigger_delta;
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unmask_interrupt(INT_PIT);
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spin_unlock_irqrestore(&lock, state);
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return NO_ERROR;
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}
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status_t pit_set_oneshot_timer(platform_timer_callback callback, void *arg, lk_time_t interval) {
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LTRACEF("pit_set_oneshot_timer: interval %u\n", interval);
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spin_lock_saved_state_t state;
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spin_lock_irqsave(&lock, state);
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t_callback = callback;
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callback_arg = arg;
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next_trigger_delta = 0;
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next_trigger_time = timer_current_time + ((uint64_t)interval << 32);
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unmask_interrupt(INT_PIT);
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spin_unlock_irqrestore(&lock, state);
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return NO_ERROR;
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}
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void pit_cancel_timer(void) {
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LTRACE;
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spin_lock_saved_state_t state;
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spin_lock_irqsave(&lock, state);
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next_trigger_time = 0;
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spin_unlock_irqrestore(&lock, state);
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}
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void pit_stop_timer(void) {
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LTRACE;
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spin_lock_saved_state_t state;
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spin_lock_irqsave(&lock, state);
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next_trigger_time = 0;
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next_trigger_delta = 0;
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// stop the PIT
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outp(I8253_CONTROL_REG, 0x34);
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outp(I8253_DATA_REG, 0); // LSB
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outp(I8253_DATA_REG, 0); // MSB
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mask_interrupt(INT_PIT);
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spin_unlock_irqrestore(&lock, state);
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}
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uint64_t pit_calibrate_tsc(void) {
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DEBUG_ASSERT(arch_ints_disabled());
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uint64_t tsc_ticks[5] = {0};
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uint32_t countdown_ms[5] = {0};
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uint64_t tsc_freq = 0;
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for (uint i = 0; i < countof(tsc_ticks); i++) {
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// calibrate the tsc frequency using the PIT
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countdown_ms[i] = 2 * (i + 1);
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uint16_t pic_ticks = INTERNAL_FREQ_TICKS_PER_MS * countdown_ms[i];
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outp(I8253_CONTROL_REG, 0x30);
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outp(I8253_DATA_REG, pic_ticks & 0xff); // LSB
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outp(I8253_DATA_REG, pic_ticks >> 8); // MSB
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// read the tsc
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uint64_t tsc_start = __builtin_ia32_rdtsc();
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// wait for countdown_ms
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uint8_t status = 0;
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do {
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// Send a read-back command that latches the status of ch0
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outp(I8253_CONTROL_REG, 0xe2);
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status = inp(I8253_DATA_REG);
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// Wait for bit 7 (output) to go high and for bit 6 (null count) to go low
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} while ((status & 0xc0) != 0x80);
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uint64_t tsc_end = __builtin_ia32_rdtsc();
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tsc_ticks[i] = tsc_end - tsc_start;
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}
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// find the best time
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uint best_index = 0;
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for (uint i = 1; i < countof(tsc_ticks); i++) {
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if (tsc_ticks[i] < tsc_ticks[best_index]) {
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best_index = i;
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}
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}
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// calculate the tsc frequency
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tsc_freq = (tsc_ticks[best_index] * 1000) / countdown_ms[best_index];
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dprintf(INFO, "PIT: calibrated TSC frequency: %" PRIu64 "Hz\n", tsc_freq);
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// put the PIT back to 1ms countdown
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set_pit_frequency(1000);
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return tsc_freq;
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}
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uint32_t pit_calibrate_lapic(uint32_t (*lapic_read_tick)(void)) {
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DEBUG_ASSERT(arch_ints_disabled());
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uint64_t lapic_ticks[5] = {0};
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uint32_t countdown_ms[5] = {0};
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for (uint i = 0; i < countof(lapic_ticks); i++) {
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// calibrate the tsc frequency using the PIT
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countdown_ms[i] = 2 * (i + 1);
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uint16_t pic_ticks = INTERNAL_FREQ_TICKS_PER_MS * countdown_ms[i];
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outp(I8253_CONTROL_REG, 0x30);
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outp(I8253_DATA_REG, pic_ticks & 0xff); // LSB
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outp(I8253_DATA_REG, pic_ticks >> 8); // MSB
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// read the tsc
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uint32_t tick_start = lapic_read_tick();
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// wait for countdown_ms
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uint8_t status = 0;
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do {
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// Send a read-back command that latches the status of ch0
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outp(I8253_CONTROL_REG, 0xe2);
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status = inp(I8253_DATA_REG);
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// Wait for bit 7 (output) to go high and for bit 6 (null count) to go low
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} while ((status & 0xc0) != 0x80);
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uint32_t tick_end = lapic_read_tick();
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lapic_ticks[i] = tick_start - tick_end;
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}
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// find the best time
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uint best_index = 0;
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for (uint i = 1; i < countof(lapic_ticks); i++) {
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if (lapic_ticks[i] < lapic_ticks[best_index]) {
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best_index = i;
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}
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}
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// calculate the tsc frequency
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uint32_t freq = (lapic_ticks[best_index] * 1000) / countdown_ms[best_index];
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dprintf(INFO, "PIT: calibrated local apic frequency: %" PRIu32 "Hz\n", freq);
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// put the PIT back to 1ms countdown
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set_pit_frequency(1000);
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return freq;
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} |