bce9599d80
It is possible for early initialization functions such as lk_main() to contain NEON instructions because we don't build the kernel with -mgeneral-regs-only. As a result we can end up taking an FPU exception before we are ready to handle it. We didn't have this problem when starting at a higher exception level than EL1 because we turned off FPU traps in arm64_elX_to_el1(). But we neglected to do so when starting at EL1. Fix the problem by moving the CPACR_EL1 manipulation out of arm64_elX_to_el1() and into arm_reset().
129 lines
2.4 KiB
ArmAsm
129 lines
2.4 KiB
ArmAsm
/*
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* Copyright (c) 2014 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include <lk/asm.h>
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#include <arch/asm_macros.h>
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/* void arm64_context_switch(vaddr_t *old_sp, vaddr_t new_sp); */
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FUNCTION(arm64_context_switch)
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/* save old frame */
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push x28, x29
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push x26, x27
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push x24, x25
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push x22, x23
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push x20, x21
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push x18, x19
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mrs x18, tpidr_el0
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mrs x19, tpidrro_el0
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push x18, x19
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push x30, xzr
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/* save old sp */
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mov x15, sp
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str x15, [x0]
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/* load new sp */
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mov sp, x1
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/* restore new frame */
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pop x30, xzr
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pop x18, x19
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msr tpidr_el0, x18
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msr tpidrro_el0, x19
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pop x18, x19
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pop x20, x21
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pop x22, x23
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pop x24, x25
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pop x26, x27
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pop x28, x29
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ret
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FUNCTION(arm64_el3_to_el1)
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/* set EL2 to 64bit */
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mrs x0, scr_el3
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orr x0, x0, #(1<<10)
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msr scr_el3, x0
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/* set EL1 to 64bit */
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mov x0, #(1<<31)
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msr hcr_el2, x0
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/* disable EL2 coprocessor traps */
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mov x0, #0x33ff
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msr cptr_el2, x0
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/* disable EL1 FPU traps */
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mov x0, #(0b11<<20)
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msr cpacr_el1, x0
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/* set up the EL1 bounce interrupt */
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mov x0, sp
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msr sp_el1, x0
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adr x0, .Ltarget
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msr elr_el3, x0
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mov x0, #((0b1111 << 6) | (0b0101)) /* EL1h runlevel */
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msr spsr_el3, x0
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isb
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eret
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/* drop from whatever EL we may already be in to EL1.
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* carefully avoids using x0-x3 since this is called from start.S
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* which is trying to preserve them.
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*/
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FUNCTION(arm64_elX_to_el1)
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mrs x4, CurrentEL
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cmp x4, #(0b01 << 2)
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bne .notEL1
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/* Already in EL1 */
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ret
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.notEL1:
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cmp x4, #(0b10 << 2)
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beq .inEL2
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/* set EL2 to 64bit */
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mrs x4, scr_el3
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orr x4, x4, #(1<<10)
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msr scr_el3, x4
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adr x4, .Ltarget
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msr elr_el3, x4
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mov x4, #((0b1111 << 6) | (0b0101)) /* EL1h runlevel */
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msr spsr_el3, x4
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b .confEL1
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.inEL2:
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adr x4, .Ltarget
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msr elr_el2, x4
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mov x4, #((0b1111 << 6) | (0b0101)) /* EL1h runlevel */
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msr spsr_el2, x4
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.confEL1:
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/* disable EL2 coprocessor traps */
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mov x4, #0x33ff
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msr cptr_el2, x4
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/* set EL1 to 64bit */
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mov x4, #(1<<31)
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msr hcr_el2, x4
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/* set up the EL1 bounce interrupt */
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mov x4, sp
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msr sp_el1, x4
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isb
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eret
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.Ltarget:
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ret
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