Zhong,Fangjian 4b4e68bb29 [arch][x86] update x86 TSS and IDT ...

1. Update TSS selector description.
2. Enlarge TSS selector up to SMP_MAX_CPUS.
3. Enlarge interrupt numbers support to 0xFF in arch x86-64.

Signed-off-by: Zhong,Fangjian <fangjian.zhong@intel.com>

2017-11-08 08:29:23 +08:00

..

arm

[arch][arm] disable alignment aborts

2017-02-06 18:54:11 -08:00

arm64

[arch][arm64] change CACHE_LINE to 64 for cortex a53,57 and 72

2017-06-05 10:41:45 -07:00

microblaze

[spelling] spelling-fixes. (not external/)

2016-08-25 17:30:34 -07:00

mips

[spelling] spelling-fixes. (not external/)

2016-08-25 17:30:34 -07:00

or1k

[spelling] spelling-fixes. (not external/)

2016-08-25 17:30:34 -07:00

x86

[arch][x86] update x86 TSS and IDT

2017-11-08 08:29:23 +08:00