e9079cb7ee
This seems to happen if the device had not been frobbed by any firmware prior to handing off to the system. Seems that a proper reset is in order, but for now simply ignore it, assume it's a disk, and continue.
272 lines
8.7 KiB
C++
272 lines
8.7 KiB
C++
//
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// Copyright (c) 2022 Travis Geiselbrecht
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//
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// Use of this source code is governed by a MIT-style
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// license that can be found in the LICENSE file or at
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// https://opensource.org/licenses/MIT
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#include "port.h"
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#include <lk/bits.h>
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#include <lk/err.h>
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#include <lk/trace.h>
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#include <kernel/vm.h>
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#include <kernel/thread.h>
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#include <string.h>
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#include "ata.h"
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#include "disk.h"
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#define LOCAL_TRACE 1
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ahci_port::ahci_port(ahci &a, uint num) : ahci_(a), num_(num) {
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for (auto &e : cmd_complete_event_) {
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event_init(&e, false, EVENT_FLAG_AUTOUNSIGNAL);
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}
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}
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ahci_port::~ahci_port() {
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if (mem_region_) {
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vmm_free_region(vmm_get_kernel_aspace(), (vaddr_t)mem_region_);
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}
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for (auto &e : cmd_complete_event_) {
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event_destroy(&e);
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}
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}
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status_t ahci_port::probe(ahci_disk **found_disk) {
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// mask all IRQS on this port regardless if we want to use it
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write_port_reg(ahci_port_reg::PxIE, 0);
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// clear any pending bits
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write_port_reg(ahci_port_reg::PxIS, 0xffffffff);
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// check if drive is present
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auto ssts = read_port_reg(ahci_port_reg::PxSSTS);
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if (BITS(ssts, 3, 0) != 3) { // check SSTS.DET == 3 (device present and phy comm established)
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return ERR_NOT_FOUND;
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}
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if (BITS_SHIFT(ssts, 11, 8) != 1) { // check SSTS.IPM == 1 (interface in active state)
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return ERR_NOT_FOUND;
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}
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dprintf(INFO, "ahci%d port %u: ssts %#x device present and interface in active state\n",
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ahci_.get_unit_num(), num_, ssts);
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auto sig = read_port_reg(ahci_port_reg::PxSIG);
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LTRACEF("port %u: sig %#x\n", num_, sig);
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// if sig is all 1s then it hasn't been scanned yet, so assume it's a disk.
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// otherwise if its 0x101 it's a disk
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if (sig != 0xffffffff && sig != 0x101) {
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TRACEF("skipping unhandled signature %#x\n", sig);
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return ERR_NOT_FOUND;
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}
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LTRACEF("port %u: PxCLB %#x\n", num_, read_port_reg(ahci_port_reg::PxCLB));
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LTRACEF("port %u: PxCMD %#x\n", num_, read_port_reg(ahci_port_reg::PxCMD));
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// stop the port so we can reset addresses
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auto cmd_reg = read_port_reg(ahci_port_reg::PxCMD);
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cmd_reg &= ~((1<<4) | // clear CMD.FRE (fis receive enable)
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(1<<0)); // clear CMD.ST (start)
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write_port_reg(ahci_port_reg::PxCMD, cmd_reg);
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// TODO: wait for CMD.FR to stop
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// allocate a block of contiguous memory for
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// 32 command list heads (32 * 0x20)
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// a FIS struct (256 bytes)
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// 32 command tables with 16 PRDTs per
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const size_t size = (CMD_COUNT * sizeof(ahci_cmd_header)) + 256 +
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(CMD_COUNT * CMD_TABLE_ENTRY_SIZE);
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// allocate a contiguous block of ram
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char str[32];
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snprintf(str, sizeof(str), "ahci%d.%u cmd/fis", ahci_.get_unit_num(), num_);
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status_t err = vmm_alloc_contiguous(vmm_get_kernel_aspace(), str, size,
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(void **)&mem_region_, 0, /* vmm_flags */ 0,
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ARCH_MMU_FLAG_UNCACHED_DEVICE);
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if (err != NO_ERROR) {
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return ERR_NOT_FOUND;
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}
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memset(mem_region_, 0, size);
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mem_region_paddr_ = vaddr_to_paddr(mem_region_);
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LTRACEF("cmd_list/fis mapped to %p, pa %#lx\n", mem_region_, mem_region_paddr_);
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// carve up the pointers into this space
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cmd_list_ = (volatile ahci_cmd_header *)mem_region_;
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fis_ = (volatile uint8_t *)((uintptr_t)mem_region_ + 32 * sizeof(ahci_cmd_header));
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cmd_table_ = (volatile ahci_cmd_table *)(fis_ + 256);
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LTRACEF("command list at %p, FIS at %p, per command table at %p\n",
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cmd_list_, fis_, cmd_table_);
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// set the AHCI port to point to the command header and global fis
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write_port_reg(ahci_port_reg::PxCLB, vaddr_to_paddr((void *)cmd_list_));
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write_port_reg(ahci_port_reg::PxFB, vaddr_to_paddr((void *)fis_));
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#if __INTPTR_WIDTH__ == 64
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write_port_reg(ahci_port_reg::PxCLBU, vaddr_to_paddr((void *)cmd_list_) >> 32);
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write_port_reg(ahci_port_reg::PxFBU, vaddr_to_paddr((void *)fis_) >> 32);
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#else
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write_port_reg(ahci_port_reg::PxCLBU, 0);
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write_port_reg(ahci_port_reg::PxFBU, 0);
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#endif
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// set up the command headers
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auto cmd_table_pa = vaddr_to_paddr((void *)cmd_table_);
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for (auto i = 0; i < 32; i++) {
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volatile auto *cmd = &cmd_list_[i];
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// point the cmd header at the corresponding cmd table
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cmd->ctba = (cmd_table_pa + sizeof(ahci_cmd_table) * i) & 0xffffffff;
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#if __INTPTR_WIDTH__ == 64
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cmd->ctbau = (cmd_table_pa + sizeof(ahci_cmd_table) * i) >> 32;
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#else
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cmd->ctbau = 0;
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#endif
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}
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// restart the port
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cmd_reg |= (1<<4); // set CMD.FRE (fis receive enable)
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write_port_reg(ahci_port_reg::PxCMD, cmd_reg);
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cmd_reg |= (1<<0); // set CMD.ST (start)
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write_port_reg(ahci_port_reg::PxCMD, cmd_reg);
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// unmask some irqs on this port
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// TODO: unmask more if needed
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uint32_t ie = (1U << 5) | // Descriptor Processed (DPS)
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(1U << 3) | // Set device bits interrupt (SDBS)
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(1U << 2) | // DMA setup FIS (DSS)
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(1U << 1) | // PIO setup FIS (PSS)
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(1U << 0); // Device to Host Register FIS (DHRS)
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write_port_reg(ahci_port_reg::PxIE, ie);
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// we found a disk above, create an object and pass it back
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auto *disk = new ahci_disk(*this);
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*found_disk = disk;
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return NO_ERROR;
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}
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int ahci_port::find_free_cmdslot() {
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uint32_t all_slots = read_port_reg(ahci_port_reg::PxSACT) |
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read_port_reg(ahci_port_reg::PxCI);
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LTRACEF("all_slots %#x\n", all_slots);
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if (unlikely(all_slots == 0xffffffff)) {
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// all slots are full
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return -1;
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}
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int avail = __builtin_clz(~all_slots);
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LTRACEF("avail %u\n", avail);
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return avail;
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}
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status_t ahci_port::queue_command(const void *fis, size_t fis_len, void *buf, size_t buf_len, bool write, int *slot_out) {
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LTRACEF("fis %p len %zu buf %p len %zu write %d\n", fis, fis_len, buf, buf_len, write);
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DEBUG_ASSERT(fis);
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DEBUG_ASSERT(fis_len > 0 && fis_len <= 64 && IS_ALIGNED(fis_len, 4));
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DEBUG_ASSERT(buf || buf_len == 0);
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AutoSpinLock guard(&lock_);
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auto slot = find_free_cmdslot();
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LTRACEF("slot %u\n", slot);
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// clear interrupt status for this port
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write_port_reg(ahci_port_reg::PxIS, 0xf);
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auto *cmd_table = cmd_table_ptr(slot);
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// set up physical descriptor of a run of memory
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// XXX for now assume single run
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auto *prdt = &cmd_table->pdrt[0];
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auto buf_pa = vaddr_to_paddr(buf);
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prdt->dba = buf_pa;
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#if __INTPTR_WIDTH__ == 64
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prdt->dbau = buf_pa >> 32;
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#else
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prdt->dbau = 0;
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#endif
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prdt->byte_count_ioc = (buf_len - 1) | (1U<<31); // byte count, interrupt on completion
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// copy command into the command table
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// TODO: replace with wordwise copy
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memcpy((void *)cmd_table->cfis, fis, fis_len);
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// set up the command header
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auto *cmd = &cmd_list_[slot];
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cmd->cmd = (fis_len / sizeof(uint32_t)) | (write ? (1<<6) : (0<<6)); // command fis size in words, read/write from device
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cmd->prdtl = 1; // 1 prdt
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//LTRACEF("cmd_table %p\n", cmd_table);
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//hexdump((const void *)cmd_table, sizeof(*cmd_table) + CMD_TABLE_ENTRY_SIZE);
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// TODO: barrier here
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// rmb();
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LTRACEF("IS %#x (before kick)\n", read_port_reg(ahci_port_reg::PxIS));
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cmd_pending_ |= (1U << slot);
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// kick the command
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write_port_reg(ahci_port_reg::PxCI, (1U << slot)); // TODO: RMW?
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*slot_out = slot;
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return NO_ERROR;
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}
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status_t ahci_port::wait_for_completion(int slot) {
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DEBUG_ASSERT(slot >= 0 && slot < (int)CMD_COUNT);
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auto err = event_wait(&cmd_complete_event_[slot]);
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return err;
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}
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handler_return ahci_port::irq_handler() {
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LTRACE_ENTRY;
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AutoSpinLockNoIrqSave guard(&lock_);
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const auto raw_is = read_port_reg(ahci_port_reg::PxIS);
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const auto is = raw_is & read_port_reg(ahci_port_reg::PxIE); // filter by things we're masking
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LTRACEF("raw is %#x is %#x\n", raw_is, is);
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// see if any commands completed
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const auto ci = read_port_reg(ahci_port_reg::PxCI);
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auto cmd_complete_bitmap = cmd_pending_ & ~ci;
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LTRACEF("command complete bitmap %#x\n", cmd_complete_bitmap);
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handler_return ret = INT_NO_RESCHEDULE;
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while (cmd_complete_bitmap != 0) {
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const size_t cmd_slot = __builtin_ctz(cmd_complete_bitmap);
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DEBUG_ASSERT(cmd_slot < CMD_COUNT);
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LTRACEF("slot %zu completed\n", cmd_slot);
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// this slot completed
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event_signal(&cmd_complete_event_[cmd_slot], false);
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ret = INT_RESCHEDULE;
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// mark the command as not pending anymore
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cmd_pending_ &= ~(1U << cmd_slot);
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// move to the next pending slot (if any)
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cmd_complete_bitmap &= ~(1U << cmd_slot);
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}
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// ack everything for now
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write_port_reg(ahci_port_reg::PxIS, is);
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return ret;
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}
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