322 lines
12 KiB
C
322 lines
12 KiB
C
/*
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* Copyright (c) 2015 Travis Geiselbrecht
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files
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* (the "Software"), to deal in the Software without restriction,
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* including without limitation the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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/*
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* COPYRIGHT(c) 2015 STMicroelectronics
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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#include <err.h>
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#include <debug.h>
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#include <trace.h>
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#include <target.h>
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#include <compiler.h>
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#include <dev/gpio.h>
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#include <platform/stm32.h>
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/*
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* sdram initialization sequence, taken from
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* STM32Cube_FW_F7_V1.1.0/Drivers/BSP/STM32756G_EVAL/stm32756g_eval_sdram.[ch]
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*/
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/**
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* @brief SDRAM status structure definition
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*/
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#define SDRAM_OK ((uint8_t)0x00)
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#define SDRAM_ERROR ((uint8_t)0x01)
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/** @defgroup STM32756G_EVAL_SDRAM_Exported_Constants
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* @{
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*/
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#define SDRAM_DEVICE_ADDR ((uint32_t)0xC0000000)
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#define SDRAM_DEVICE_SIZE ((uint32_t)0x800000) /* SDRAM device size in MBytes */
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/* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_8 */
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/* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_16 */
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#define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_32
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#define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2
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/* #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_3 */
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#define REFRESH_COUNT ((uint32_t)0x0603) /* SDRAM refresh counter (100Mhz SD clock) */
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#define SDRAM_TIMEOUT ((uint32_t)0xFFFF)
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/* DMA definitions for SDRAM DMA transfer */
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#define __DMAx_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
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#define __DMAx_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
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#define SDRAM_DMAx_CHANNEL DMA_CHANNEL_0
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#define SDRAM_DMAx_STREAM DMA2_Stream0
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#define SDRAM_DMAx_IRQn DMA2_Stream0_IRQn
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#define SDRAM_DMAx_IRQHandler DMA2_Stream0_IRQHandler
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/**
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* @}
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*/
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/**
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* @brief FMC SDRAM Mode definition register defines
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*/
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#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
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#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
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#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
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#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
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#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
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#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
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#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
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#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
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#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
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#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
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#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
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static SDRAM_HandleTypeDef sdramHandle;
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/**
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* @brief Initializes SDRAM MSP.
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* @param hsdram: SDRAM handle
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* @retval None
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*/
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static void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
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{
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static DMA_HandleTypeDef dma_handle;
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GPIO_InitTypeDef gpio_init_structure;
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/* Enable FMC clock */
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__HAL_RCC_FMC_CLK_ENABLE();
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/* Enable chosen DMAx clock */
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__DMAx_CLK_ENABLE();
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/* Enable GPIOs clock */
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__HAL_RCC_GPIOD_CLK_ENABLE();
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__HAL_RCC_GPIOE_CLK_ENABLE();
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__HAL_RCC_GPIOF_CLK_ENABLE();
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__HAL_RCC_GPIOG_CLK_ENABLE();
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__HAL_RCC_GPIOH_CLK_ENABLE();
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__HAL_RCC_GPIOI_CLK_ENABLE();
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/* Common GPIO configuration */
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gpio_init_structure.Mode = GPIO_MODE_AF_PP;
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gpio_init_structure.Pull = GPIO_PULLUP;
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gpio_init_structure.Speed = GPIO_SPEED_FAST;
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gpio_init_structure.Alternate = GPIO_AF12_FMC;
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/* GPIOD configuration */
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gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8| GPIO_PIN_9 | GPIO_PIN_10 |\
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GPIO_PIN_14 | GPIO_PIN_15;
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HAL_GPIO_Init(GPIOD, &gpio_init_structure);
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/* GPIOE configuration */
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gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\
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GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
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GPIO_PIN_15;
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HAL_GPIO_Init(GPIOE, &gpio_init_structure);
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/* GPIOF configuration */
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gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
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GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
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GPIO_PIN_15;
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HAL_GPIO_Init(GPIOF, &gpio_init_structure);
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/* GPIOG configuration */
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gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\
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GPIO_PIN_15;
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HAL_GPIO_Init(GPIOG, &gpio_init_structure);
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/* GPIOH configuration */
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gpio_init_structure.Pin = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_9 |\
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GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
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GPIO_PIN_15;
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HAL_GPIO_Init(GPIOH, &gpio_init_structure);
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/* GPIOI configuration */
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gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 |\
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GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_9 | GPIO_PIN_10;
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HAL_GPIO_Init(GPIOI, &gpio_init_structure);
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/* Configure common DMA parameters */
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dma_handle.Init.Channel = SDRAM_DMAx_CHANNEL;
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dma_handle.Init.Direction = DMA_MEMORY_TO_MEMORY;
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dma_handle.Init.PeriphInc = DMA_PINC_ENABLE;
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dma_handle.Init.MemInc = DMA_MINC_ENABLE;
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dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
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dma_handle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
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dma_handle.Init.Mode = DMA_NORMAL;
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dma_handle.Init.Priority = DMA_PRIORITY_HIGH;
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dma_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
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dma_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
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dma_handle.Init.MemBurst = DMA_MBURST_SINGLE;
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dma_handle.Init.PeriphBurst = DMA_PBURST_SINGLE;
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dma_handle.Instance = SDRAM_DMAx_STREAM;
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/* Associate the DMA handle */
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__HAL_LINKDMA(hsdram, hdma, dma_handle);
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/* Deinitialize the stream for new transfer */
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HAL_DMA_DeInit(&dma_handle);
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/* Configure the DMA stream */
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HAL_DMA_Init(&dma_handle);
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#if 0
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/* NVIC configuration for DMA transfer complete interrupt */
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HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn);
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#endif
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}
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/**
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* @brief Programs the SDRAM device.
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* @param RefreshCount: SDRAM refresh counter value
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* @retval None
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*/
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static void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount)
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{
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__IO uint32_t tmpmrd = 0;
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FMC_SDRAM_CommandTypeDef Command;
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/* Step 1: Configure a clock configuration enable command */
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Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
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Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
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Command.AutoRefreshNumber = 1;
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Command.ModeRegisterDefinition = 0;
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/* Send the command */
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HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
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/* Step 2: Insert 100 us minimum delay */
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spin(1000);
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/* Step 3: Configure a PALL (precharge all) command */
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Command.CommandMode = FMC_SDRAM_CMD_PALL;
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Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
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Command.AutoRefreshNumber = 1;
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Command.ModeRegisterDefinition = 0;
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/* Send the command */
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HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
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/* Step 4: Configure an Auto Refresh command */
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Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
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Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
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Command.AutoRefreshNumber = 8;
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Command.ModeRegisterDefinition = 0;
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/* Send the command */
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HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
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/* Step 5: Program the external memory mode register */
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tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\
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SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\
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SDRAM_MODEREG_CAS_LATENCY_3 |\
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SDRAM_MODEREG_OPERATING_MODE_STANDARD |\
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SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
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Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
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Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
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Command.AutoRefreshNumber = 1;
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Command.ModeRegisterDefinition = tmpmrd;
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/* Send the command */
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HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
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/* Step 6: Set the refresh rate counter */
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/* Set the device refresh rate */
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HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount);
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}
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/**
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* @brief Initializes the SDRAM device.
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* @retval SDRAM status
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*/
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uint8_t BSP_SDRAM_Init(void)
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{
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static uint8_t sdramstatus = SDRAM_ERROR;
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/* SDRAM device configuration */
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sdramHandle.Instance = FMC_SDRAM_DEVICE;
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/* Timing configuration for 100Mhz as SDRAM clock frequency (System clock is up to 200Mhz) */
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FMC_SDRAM_TimingTypeDef Timing;
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Timing.LoadToActiveDelay = 2;
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Timing.ExitSelfRefreshDelay = 7;
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Timing.SelfRefreshTime = 4;
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Timing.RowCycleDelay = 7;
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Timing.WriteRecoveryTime = 2;
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Timing.RPDelay = 2;
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Timing.RCDDelay = 2;
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sdramHandle.Init.SDBank = FMC_SDRAM_BANK1;
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sdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9;
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sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
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sdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH;
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sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
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sdramHandle.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3;
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sdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
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sdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD;
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sdramHandle.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;
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sdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
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/* SDRAM controller initialization */
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BSP_SDRAM_MspInit(&sdramHandle);
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if (HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK) {
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sdramstatus = SDRAM_ERROR;
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} else {
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sdramstatus = SDRAM_OK;
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}
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/* SDRAM initialization sequence */
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BSP_SDRAM_Initialization_sequence(REFRESH_COUNT);
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return sdramstatus;
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}
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