36e73e0fac
Wire them up on arm and riscv which need them. x86-pc does not, so dont call it. Also fix a few miscellaneous bugs, notably PCI not detecting 64bit bars properly due to an off by one bit error.
300 lines
10 KiB
C++
300 lines
10 KiB
C++
/*
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* Copyright (c) 2009 Corey Tabaka
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* Copyright (c) 2020 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include <dev/bus/pci.h>
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#include <lk/debug.h>
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#include <lk/err.h>
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#include <stdlib.h>
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#include <string.h>
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#include <kernel/thread.h>
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#include <kernel/spinlock.h>
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#include <lk/trace.h>
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#include "pci_priv.h"
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#define LOCAL_TRACE 0
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// Largely C level api for the PCI bus manager
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namespace {
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SpinLock lock;
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pci_backend *pcib = nullptr;
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} // namespace
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/* user facing routines */
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int pci_get_last_bus() {
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if (!pcib) {
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return ERR_NOT_CONFIGURED;
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}
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return pcib->get_last_bus();
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}
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int pci_get_last_segment() {
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// currently hard coded to 1 segment
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return 0;
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}
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status_t pci_read_config_byte(const pci_location_t state, uint32_t reg, uint8_t *value) {
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if (!pcib) return ERR_NOT_CONFIGURED;
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AutoSpinLock guard(&lock);
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int res = pcib->read_config_byte(state, reg, value);
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return res;
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}
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status_t pci_read_config_half(const pci_location_t state, uint32_t reg, uint16_t *value) {
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if (!pcib) return ERR_NOT_CONFIGURED;
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AutoSpinLock guard(&lock);
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int res = pcib->read_config_half(state, reg, value);
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return res;
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}
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status_t pci_read_config_word(const pci_location_t state, uint32_t reg, uint32_t *value) {
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if (!pcib) return ERR_NOT_CONFIGURED;
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AutoSpinLock guard(&lock);
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int res = pcib->read_config_word(state, reg, value);
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return res;
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}
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status_t pci_write_config_byte(const pci_location_t state, uint32_t reg, uint8_t value) {
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if (!pcib) return ERR_NOT_CONFIGURED;
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AutoSpinLock guard(&lock);
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int res = pcib->write_config_byte(state, reg, value);
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return res;
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}
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status_t pci_write_config_half(const pci_location_t state, uint32_t reg, uint16_t value) {
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if (!pcib) return ERR_NOT_CONFIGURED;
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AutoSpinLock guard(&lock);
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int res = pcib->write_config_half(state, reg, value);
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return res;
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}
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status_t pci_write_config_word(const pci_location_t state, uint32_t reg, uint32_t value) {
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if (!pcib) return ERR_NOT_CONFIGURED;
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AutoSpinLock guard(&lock);
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int res = pcib->write_config_word(state, reg, value);
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return res;
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}
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status_t pci_read_config(const pci_location_t loc, pci_config_t *config) {
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status_t err;
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*config = {};
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// TODO: handle endian swapping (if necessary)
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// define some helper routines to read config offsets in the proper unit
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size_t next_index;
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auto read_byte = [&]() -> uint8_t {
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uint8_t val;
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err = pci_read_config_byte(loc, next_index, &val);
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next_index++;
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if (err < 0) return 0;
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return val;
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};
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auto read_half = [&]() -> uint16_t {
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uint16_t val;
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err = pci_read_config_half(loc, next_index, &val);
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next_index += 2;
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if (err < 0) return 0;
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return val;
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};
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auto read_word = [&]() -> uint32_t {
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uint32_t val;
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err = pci_read_config_word(loc, next_index, &val);
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next_index += 4;
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if (err < 0) return 0;
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return val;
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};
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// shared, standard part of the pci config space
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/*
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uint16_t vendor_id;
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uint16_t device_id;
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uint16_t command;
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uint16_t status;
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uint8_t revision_id_0;
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uint8_t program_interface;
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uint8_t sub_class;
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uint8_t base_class;
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uint8_t cache_line_size;
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uint8_t latency_timer;
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uint8_t header_type;
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uint8_t bist;
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*/
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next_index = 0;
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config->vendor_id = read_half(); if (err < 0) return err;
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config->device_id = read_half(); if (err < 0) return err;
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config->command = read_half(); if (err < 0) return err;
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config->status = read_half(); if (err < 0) return err;
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config->revision_id_0 = read_byte(); if (err < 0) return err;
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config->program_interface = read_byte(); if (err < 0) return err;
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config->sub_class = read_byte(); if (err < 0) return err;
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config->base_class = read_byte(); if (err < 0) return err;
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config->cache_line_size = read_byte(); if (err < 0) return err;
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config->latency_timer = read_byte(); if (err < 0) return err;
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config->header_type = read_byte(); if (err < 0) return err;
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config->bist = read_byte(); if (err < 0) return err;
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DEBUG_ASSERT(next_index == 0x10); // should have read this many bytes at this point
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// based on the type field, read two different types
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const uint8_t type = config->header_type & 0x7f;
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if (type == 0) {
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/*
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uint32_t base_addresses[6];
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uint32_t cardbus_cis_ptr;
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uint16_t subsystem_vendor_id;
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uint16_t subsystem_id;
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uint32_t expansion_rom_address;
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uint8_t capabilities_ptr;
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uint8_t reserved_0[3];
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uint32_t reserved_1;
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uint8_t interrupt_line;
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uint8_t interrupt_pin;
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uint8_t min_grant;
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uint8_t max_latency;
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*/
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config->type0.base_addresses[0] = read_word(); if (err < 0) return err;
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config->type0.base_addresses[1] = read_word(); if (err < 0) return err;
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config->type0.base_addresses[2] = read_word(); if (err < 0) return err;
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config->type0.base_addresses[3] = read_word(); if (err < 0) return err;
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config->type0.base_addresses[4] = read_word(); if (err < 0) return err;
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config->type0.base_addresses[5] = read_word(); if (err < 0) return err;
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config->type0.cardbus_cis_ptr = read_word(); if (err < 0) return err;
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config->type0.subsystem_vendor_id = read_half(); if (err < 0) return err;
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config->type0.subsystem_id = read_half(); if (err < 0) return err;
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config->type0.expansion_rom_address = read_word(); if (err < 0) return err;
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config->type0.capabilities_ptr = read_byte(); if (err < 0) return err;
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next_index += 3 + 4; // 7 bytes of reserved space
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config->type0.interrupt_line = read_byte(); if (err < 0) return err;
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config->type0.interrupt_pin = read_byte(); if (err < 0) return err;
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config->type0.min_grant = read_byte(); if (err < 0) return err;
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config->type0.max_latency = read_byte(); if (err < 0) return err;
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DEBUG_ASSERT(next_index == 0x40); // should have read this many bytes at this point
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} else if (type == 1) {
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/*
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uint32_t base_addresses[2];
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uint8_t primary_bus;
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uint8_t secondary_bus;
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uint8_t subordinate_bus;
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uint8_t secondary_latency_timer;
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uint8_t io_base;
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uint8_t io_limit;
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uint16_t secondary_status;
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uint16_t memory_base;
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uint16_t memory_limit;
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uint16_t prefetchable_memory_base;
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uint16_t prefetchable_memory_limit;
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uint32_t prefetchable_base_upper;
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uint32_t prefetchable_limit_upper;
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uint16_t io_base_upper;
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uint16_t io_limit_upper;
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uint8_t capabilities_ptr;
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uint8_t reserved_0[3];
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uint32_t expansion_rom_address;
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uint8_t interrupt_line;
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uint8_t interrupt_pin;
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uint16_t bridge_control;
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*/
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config->type1.base_addresses[0] = read_word(); if (err < 0) return err;
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config->type1.base_addresses[1] = read_word(); if (err < 0) return err;
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config->type1.primary_bus = read_byte(); if (err < 0) return err;
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config->type1.secondary_bus = read_byte(); if (err < 0) return err;
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config->type1.subordinate_bus = read_byte(); if (err < 0) return err;
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config->type1.secondary_latency_timer = read_byte(); if (err < 0) return err;
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config->type1.io_base = read_byte(); if (err < 0) return err;
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config->type1.io_limit = read_byte(); if (err < 0) return err;
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config->type1.secondary_status = read_half(); if (err < 0) return err;
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config->type1.memory_base = read_half(); if (err < 0) return err;
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config->type1.memory_limit = read_half(); if (err < 0) return err;
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config->type1.prefetchable_memory_base = read_half(); if (err < 0) return err;
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config->type1.prefetchable_memory_limit = read_half(); if (err < 0) return err;
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config->type1.prefetchable_base_upper = read_word(); if (err < 0) return err;
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config->type1.prefetchable_limit_upper = read_word(); if (err < 0) return err;
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config->type1.io_base_upper = read_half(); if (err < 0) return err;
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config->type1.io_limit_upper = read_half(); if (err < 0) return err;
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config->type1.capabilities_ptr = read_byte(); if (err < 0) return err;
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next_index += 3; // 3 reserved bytes
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config->type1.expansion_rom_address = read_word(); if (err < 0) return err;
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config->type1.interrupt_line = read_byte(); if (err < 0) return err;
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config->type1.interrupt_pin = read_byte(); if (err < 0) return err;
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config->type1.bridge_control = read_half(); if (err < 0) return err;
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DEBUG_ASSERT(next_index == 0x40); // should have read this many bytes at this point
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} else {
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// cant handle other types
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return ERR_NOT_VALID;
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}
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return NO_ERROR;
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}
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status_t pci_init_legacy() {
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LTRACE_ENTRY;
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DEBUG_ASSERT(pcib == nullptr);
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// try a series of detection mechanisms based on legacy PCI access on x86 PCs
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// try to BIOS32 access first, if present
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if ((pcib = pci_bios32::detect())) {
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dprintf(INFO, "PCI: pci bios functions installed\n");
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dprintf(INFO, "PCI: last pci bus is %d\n", pcib->get_last_bus());
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pci_bus_mgr_init();
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return NO_ERROR;
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}
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// try type 1 access
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if ((pcib = pci_type1::detect())) {
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dprintf(INFO, "PCI: pci type1 functions installed\n");
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dprintf(INFO, "PCI: last pci bus is %d\n", pcib->get_last_bus());
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pci_bus_mgr_init();
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return NO_ERROR;
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}
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// if we couldn't find anything, leave pcib null
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return ERR_NOT_FOUND;
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}
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status_t pci_init_ecam(paddr_t ecam_base, uint16_t segment, uint8_t start_bus, uint8_t end_bus) {
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LTRACEF("base %#lx, segment %hu, bus [%hhu...%hhu]\n", ecam_base, segment, start_bus, end_bus);
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DEBUG_ASSERT(pcib == nullptr);
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if ((pcib = pci_ecam::detect(ecam_base, segment, start_bus, end_bus))) {
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dprintf(INFO, "PCI: pci ecam functions installed\n");
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dprintf(INFO, "PCI: last pci bus is %d\n", pcib->get_last_bus());
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return NO_ERROR;
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}
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// if we couldn't find anything, leave pcib null
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return ERR_NOT_FOUND;
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}
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