125 lines
4.3 KiB
C
125 lines
4.3 KiB
C
/*
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* Copyright (c) 2015 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include <assert.h>
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#include <lk/trace.h>
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#include <lk/debug.h>
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#include <stdint.h>
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#include <arch/riscv.h>
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#include <arch/ops.h>
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#include <arch/mp.h>
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#include <lk/init.h>
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#include <lk/main.h>
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#include <platform.h>
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#include "riscv_priv.h"
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#define LOCAL_TRACE 0
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// per cpu structure, pointed to by xscratch
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struct riscv_percpu percpu[RISCV_MAX_HARTS];
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// called extremely early from start.S prior to getting into any other C code on
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// both the boot cpu and the secondaries
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void riscv_configure_percpu_early(uint hart_id) {
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// point xscratch at the current cpu
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// on the first cpu cpu_num should be set to 0 so we'll leave it alone
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// on secondary cpus the secondary boot code will fill in the cpu number
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riscv_csr_write(RISCV_CSR_XSCRATCH, &percpu[hart_id]);
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percpu[hart_id].hart_id = hart_id;
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}
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// first C level code to initialize each cpu
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void riscv_early_init_percpu(void) {
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// set the top level exception handler
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riscv_csr_write(RISCV_CSR_XTVEC, (uintptr_t)&riscv_exception_entry);
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// mask all exceptions, just in case
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riscv_csr_clear(RISCV_CSR_XSTATUS, RISCV_CSR_XSTATUS_IE);
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riscv_csr_clear(RISCV_CSR_XIE, RISCV_CSR_XIE_SIE | RISCV_CSR_XIE_TIE | RISCV_CSR_XIE_EIE);
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// enable cycle counter (disabled for now, unimplemented on sifive-e)
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//riscv_csr_set(mcounteren, 1);
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}
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// called very early just after entering C code on boot processor
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void arch_early_init(void) {
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riscv_early_init_percpu();
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}
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// later init per cpu
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void riscv_init_percpu(void) {
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#if WITH_SMP
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// enable software interrupts, used for inter-processor-interrupts
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riscv_csr_set(RISCV_CSR_XIE, RISCV_CSR_XIE_SIE);
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#endif
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// enable external interrupts
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riscv_csr_set(RISCV_CSR_XIE, RISCV_CSR_XIE_EIE);
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}
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// called later once the kernel is running before platform and target init
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void arch_init(void) {
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riscv_init_percpu();
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// print some arch info
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#if RISCV_M_MODE
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dprintf(INFO, "RISCV: Machine mode\n");
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dprintf(INFO, "RISCV: mvendorid %#lx marchid %#lx mimpid %#lx mhartid %#x\n",
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riscv_get_mvendorid(), riscv_get_marchid(),
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riscv_get_mimpid(), riscv_current_hart());
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dprintf(INFO, "RISCV: misa %#lx\n", riscv_csr_read(RISCV_CSR_MISA));
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#else
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dprintf(INFO, "RISCV: Supervisor mode\n");
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#if RISCV_MMU
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dprintf(INFO, "RISCV: MMU enabled sv%u\n", RISCV_MMU);
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#endif
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dprintf(INFO, "RISCV: SBI impl id %#lx version %#lx\n", sbi_call(SBI_GET_SBI_IMPL_ID).value, sbi_call(SBI_GET_SBI_IMPL_VERSION).value);
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// probe some SBI extensions
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dprintf(INFO, "RISCV: SBI extension TIMER %ld\n", sbi_call(SBI_PROBE_EXTENSION, SBI_EXT_TIMER).value);
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dprintf(INFO, "RISCV: SBI extension IPI %ld\n", sbi_call(SBI_PROBE_EXTENSION, SBI_EXT_IPI).value);
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dprintf(INFO, "RISCV: SBI extension RFENCE %ld\n", sbi_call(SBI_PROBE_EXTENSION, SBI_EXT_RFENCE).value);
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dprintf(INFO, "RISCV: SBI extension HSM %ld\n", sbi_call(SBI_PROBE_EXTENSION, SBI_EXT_HSM).value);
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dprintf(INFO, "RISCV: SBI extension SRST %ld\n", sbi_call(SBI_PROBE_EXTENSION, SBI_EXT_SRST).value);
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#endif
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#if WITH_SMP
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riscv_boot_secondaries();
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#endif
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}
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void arch_idle(void) {
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// let the platform/target disable wfi
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#if !RISCV_DISABLE_WFI
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__asm__ volatile("wfi");
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#endif
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}
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void arch_chain_load(void *entry, ulong arg0, ulong arg1, ulong arg2, ulong arg3) {
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PANIC_UNIMPLEMENTED;
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}
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/* unimplemented cache operations */
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#if RISCV_NO_CACHE_OPS
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void arch_disable_cache(uint flags) { }
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void arch_enable_cache(uint flags) { }
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void arch_clean_cache_range(addr_t start, size_t len) { }
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void arch_clean_invalidate_cache_range(addr_t start, size_t len) { }
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void arch_invalidate_cache_range(addr_t start, size_t len) { }
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void arch_sync_cache_range(addr_t start, size_t len) { }
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#else
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void arch_disable_cache(uint flags) { PANIC_UNIMPLEMENTED; }
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void arch_enable_cache(uint flags) { PANIC_UNIMPLEMENTED; }
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void arch_clean_cache_range(addr_t start, size_t len) { PANIC_UNIMPLEMENTED; }
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void arch_clean_invalidate_cache_range(addr_t start, size_t len) { PANIC_UNIMPLEMENTED; }
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void arch_invalidate_cache_range(addr_t start, size_t len) { PANIC_UNIMPLEMENTED; }
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void arch_sync_cache_range(addr_t start, size_t len) { PANIC_UNIMPLEMENTED; }
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#endif
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