7c2c8d8e56
Move a copy of the PLIC driver out of one of the platforms and make the setup of the interrupt controller a bit more dynamic.
56 lines
1.3 KiB
Makefile
56 lines
1.3 KiB
Makefile
LOCAL_DIR := $(GET_LOCAL_DIR)
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MODULE := $(LOCAL_DIR)
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ARCH := riscv
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SUBARCH ?= 32
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RISCV_MODE ?= machine
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WITH_SMP ?= true
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SMP_MAX_CPUS ?= 8
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LK_HEAP_IMPLEMENTATION ?= dlmalloc
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RISCV_FPU ?= true
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ifeq ($(RISCV_MODE),supervisor)
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ifeq ($(SUBARCH),32)
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RISCV_MMU ?= sv32
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else
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RISCV_MMU ?= sv48
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endif
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endif
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MODULE_DEPS += lib/cbuf
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MODULE_DEPS += lib/fdt
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MODULE_DEPS += lib/fdtwalk
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MODULE_DEPS += dev/bus/pci
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MODULE_DEPS += dev/bus/pci/drivers
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MODULE_DEPS += dev/interrupt/riscv_plic
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MODULE_DEPS += dev/virtio/block
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MODULE_DEPS += dev/virtio/gpu
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MODULE_DEPS += dev/virtio/net
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MODULE_SRCS += $(LOCAL_DIR)/platform.c
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MODULE_SRCS += $(LOCAL_DIR)/uart.c
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MEMBASE ?= 0x80000000
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MEMSIZE ?= 0x01000000 # default to 16MB
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ifeq ($(RISCV_MODE),supervisor)
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# offset the kernel to account for OpenSBI using the bottom
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KERNEL_LOAD_OFFSET ?= 0x00200000 # kernel load offset
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endif
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# set some global defines based on capability
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GLOBAL_DEFINES += ARCH_RISCV_CLINT_BASE=0x02000000
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GLOBAL_DEFINES += ARCH_RISCV_MTIME_RATE=10000000
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# we're going to read the default memory map from a FDT
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GLOBAL_DEFINES += NOVM_DEFAULT_ARENA=0
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# we can revert to a poll based uart spin routine
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GLOBAL_DEFINES += PLATFORM_SUPPORTS_PANIC_SHELL=1
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# do not need to implement any cache ops
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# (for now, since there are no hw accellerated qemu machines)
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GLOBAL_DEFINES += RISCV_NO_CACHE_OPS=1
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include make/module.mk
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