188 lines
8.7 KiB
C
188 lines
8.7 KiB
C
/*
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* Copyright (c) 2013-2014 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include <lk/debug.h>
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#include <lk/compiler.h>
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#include <arch/arm/cm.h>
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/* from cmsis.h */
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#if 0
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WDT_IRQn = 0, /*!< Watchdog timer Interrupt */
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WWDT_IRQn = WDT_IRQn, /*!< Watchdog timer Interrupt alias for WDT_IRQn */
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BOD_IRQn = 1, /*!< Brown Out Detect(BOD) Interrupt */
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FMC_IRQn = 2, /*!< FLASH Interrupt */
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FLASHEEPROM_IRQn = 3, /*!< EEPROM controller interrupt */
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DMA_IRQn = 4, /*!< DMA Interrupt */
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GINT0_IRQn = 5, /*!< GPIO group 0 Interrupt */
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GINT1_IRQn = 6, /*!< GPIO group 1 Interrupt */
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PIN_INT0_IRQn = 7, /*!< Pin Interrupt 0 */
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PIN_INT1_IRQn = 8, /*!< Pin Interrupt 1 */
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PIN_INT2_IRQn = 9, /*!< Pin Interrupt 2 */
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PIN_INT3_IRQn = 10, /*!< Pin Interrupt 3 */
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PIN_INT4_IRQn = 11, /*!< Pin Interrupt 4 */
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PIN_INT5_IRQn = 12, /*!< Pin Interrupt 5 */
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PIN_INT6_IRQn = 13, /*!< Pin Interrupt 6 */
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PIN_INT7_IRQn = 14, /*!< Pin Interrupt 7 */
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RITIMER_IRQn = 15, /*!< RITIMER interrupt */
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SCT0_IRQn = 16, /*!< SCT0 interrupt */
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SCT_IRQn = SCT0_IRQn, /*!< Optional alias for SCT0_IRQn */
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SCT1_IRQn = 17, /*!< SCT1 interrupt */
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SCT2_IRQn = 18, /*!< SCT2 interrupt */
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SCT3_IRQn = 19, /*!< SCT3 interrupt */
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MRT_IRQn = 20, /*!< MRT interrupt */
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UART0_IRQn = 21, /*!< UART0 Interrupt */
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UART1_IRQn = 22, /*!< UART1 Interrupt */
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UART2_IRQn = 23, /*!< UART2 Interrupt */
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I2C0_IRQn = 24, /*!< I2C0 Interrupt */
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I2C_IRQn = I2C0_IRQn, /*!< Optional alias for I2C0_IRQn */
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SPI0_IRQn = 25, /*!< SPI0 Interrupt */
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SPI1_IRQn = 26, /*!< SPI1 Interrupt */
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CAN_IRQn = 27, /*!< CAN Interrupt */
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USB0_IRQn = 28, /*!< USB IRQ interrupt */
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USB_IRQn = USB0_IRQn, /*!< Optional alias for USB0_IRQn */
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USB0_FIQ_IRQn = 29, /*!< USB FIQ interrupt */
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USB_FIQ_IRQn = USB0_FIQ_IRQn, /*!< Optional alias for USB0_FIQ_IRQn */
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USB_WAKEUP_IRQn = 30, /*!< USB wake-up interrupt Interrupt */
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ADC0_SEQA_IRQn = 31, /*!< ADC0_A sequencer Interrupt */
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ADC0_A_IRQn = ADC0_SEQA_IRQn, /*!< Optional alias for ADC0_SEQA_IRQn */
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ADC_A_IRQn = ADC0_SEQA_IRQn, /*!< Optional alias for ADC0_SEQA_IRQn */
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ADC0_SEQB_IRQn = 32, /*!< ADC0_B sequencer Interrupt */
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ADC0_B_IRQn = ADC0_SEQB_IRQn, /*!< Optional alias for ADC0_SEQB_IRQn */
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ADC_B_IRQn = ADC0_SEQB_IRQn, /*!< Optional alias for ADC0_SEQB_IRQn */
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ADC0_THCMP = 33, /*!< ADC0 threshold compare interrupt */
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ADC0_OVR = 34, /*!< ADC0 overrun interrupt */
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ADC1_SEQA_IRQn = 35, /*!< ADC1_A sequencer Interrupt */
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ADC1_A_IRQn = ADC1_SEQA_IRQn, /*!< Optional alias for ADC1_SEQA_IRQn */
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ADC1_SEQB_IRQn = 36, /*!< ADC1_B sequencer Interrupt */
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ADC1_B_IRQn = ADC1_SEQB_IRQn, /*!< Optional alias for ADC1_SEQB_IRQn */
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ADC1_THCMP = 37, /*!< ADC1 threshold compare interrupt */
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ADC1_OVR = 38, /*!< ADC1 overrun interrupt */
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DAC_IRQ = 39, /*!< DAC interrupt */
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CMP0_IRQ = 40, /*!< Analog comparator 0 interrupt */
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CMP_IRQn = CMP0_IRQ, /*!< Optional alias for CMP0_IRQ */
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CMP1_IRQ = 41, /*!< Analog comparator 1 interrupt */
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CMP2_IRQ = 42, /*!< Analog comparator 2 interrupt */
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CMP3_IRQ = 43, /*!< Analog comparator 3 interrupt */
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QEI_IRQn = 44, /*!< QEI interrupt */
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RTC_ALARM_IRQn = 45, /*!< RTC alarm interrupt */
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RTC_WAKE_IRQn = 46, /*!< RTC wake-up interrupt */
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#endif
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/* un-overridden irq handler */
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void lpc_dummy_irq(void) {
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arm_cm_irq_entry();
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panic("unhandled irq\n");
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}
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extern void lpc_uart_irq(void);
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/* a list of default handlers that are simply aliases to the dummy handler */
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#define DEFAULT_HANDLER(x) \
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void lpc_##x##_irq(void) __WEAK_ALIAS("lpc_dummy_irq")
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DEFAULT_HANDLER(WDT);
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DEFAULT_HANDLER(BOD);
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DEFAULT_HANDLER(FMC);
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DEFAULT_HANDLER(FLASHEEPROM);
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DEFAULT_HANDLER(DMA);
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DEFAULT_HANDLER(GINT0);
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DEFAULT_HANDLER(GINT1);
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DEFAULT_HANDLER(PIN_INT0);
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DEFAULT_HANDLER(PIN_INT1);
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DEFAULT_HANDLER(PIN_INT2);
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DEFAULT_HANDLER(PIN_INT3);
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DEFAULT_HANDLER(PIN_INT4);
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DEFAULT_HANDLER(PIN_INT5);
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DEFAULT_HANDLER(PIN_INT6);
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DEFAULT_HANDLER(PIN_INT7);
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DEFAULT_HANDLER(RITIMER);
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DEFAULT_HANDLER(SCT0);
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DEFAULT_HANDLER(SCT1);
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DEFAULT_HANDLER(SCT2);
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DEFAULT_HANDLER(SCT3);
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DEFAULT_HANDLER(MRT);
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DEFAULT_HANDLER(UART0);
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DEFAULT_HANDLER(UART1);
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DEFAULT_HANDLER(UART2);
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DEFAULT_HANDLER(I2C0);
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DEFAULT_HANDLER(SPI0);
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DEFAULT_HANDLER(SPI1);
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DEFAULT_HANDLER(CAN);
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DEFAULT_HANDLER(USB0);
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DEFAULT_HANDLER(USB0_FIQ);
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DEFAULT_HANDLER(USB_WAKEUP);
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DEFAULT_HANDLER(ADC0_SEQA);
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DEFAULT_HANDLER(ADC0_SEQB);
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DEFAULT_HANDLER(ADC0_THCMP);
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DEFAULT_HANDLER(ADC0_OVR);
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DEFAULT_HANDLER(ADC1_SEQA);
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DEFAULT_HANDLER(ADC1_SEQB);
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DEFAULT_HANDLER(ADC1_THCMP);
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DEFAULT_HANDLER(ADC1_OVR);
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DEFAULT_HANDLER(DAC);
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DEFAULT_HANDLER(CMP0);
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DEFAULT_HANDLER(CMP1);
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DEFAULT_HANDLER(CMP2);
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DEFAULT_HANDLER(CMP3);
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DEFAULT_HANDLER(QEI);
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DEFAULT_HANDLER(RTC_ALARM);
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DEFAULT_HANDLER(RTC_WAKE);
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#define VECTAB_ENTRY(x) lpc_##x##_irq
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const void *const __SECTION(".text.boot.vectab2") vectab2[] = {
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VECTAB_ENTRY(WDT),
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VECTAB_ENTRY(BOD),
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VECTAB_ENTRY(FMC),
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VECTAB_ENTRY(FLASHEEPROM),
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VECTAB_ENTRY(DMA),
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VECTAB_ENTRY(GINT0),
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VECTAB_ENTRY(GINT1),
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VECTAB_ENTRY(PIN_INT0),
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VECTAB_ENTRY(PIN_INT1),
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VECTAB_ENTRY(PIN_INT2),
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VECTAB_ENTRY(PIN_INT3),
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VECTAB_ENTRY(PIN_INT4),
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VECTAB_ENTRY(PIN_INT5),
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VECTAB_ENTRY(PIN_INT6),
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VECTAB_ENTRY(PIN_INT7),
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VECTAB_ENTRY(RITIMER),
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VECTAB_ENTRY(SCT0),
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VECTAB_ENTRY(SCT1),
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VECTAB_ENTRY(SCT2),
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VECTAB_ENTRY(SCT3),
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VECTAB_ENTRY(MRT),
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VECTAB_ENTRY(UART0),
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VECTAB_ENTRY(UART1),
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VECTAB_ENTRY(UART2),
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VECTAB_ENTRY(I2C0),
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VECTAB_ENTRY(SPI0),
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VECTAB_ENTRY(SPI1),
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VECTAB_ENTRY(CAN),
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VECTAB_ENTRY(USB0),
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VECTAB_ENTRY(USB0_FIQ),
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VECTAB_ENTRY(USB_WAKEUP),
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VECTAB_ENTRY(ADC0_SEQA),
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VECTAB_ENTRY(ADC0_SEQB),
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VECTAB_ENTRY(ADC0_THCMP),
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VECTAB_ENTRY(ADC0_OVR),
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VECTAB_ENTRY(ADC1_SEQA),
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VECTAB_ENTRY(ADC1_SEQB),
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VECTAB_ENTRY(ADC1_THCMP),
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VECTAB_ENTRY(ADC1_OVR),
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VECTAB_ENTRY(DAC),
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VECTAB_ENTRY(CMP0),
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VECTAB_ENTRY(CMP1),
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VECTAB_ENTRY(CMP2),
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VECTAB_ENTRY(CMP3),
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VECTAB_ENTRY(QEI),
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VECTAB_ENTRY(RTC_ALARM),
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VECTAB_ENTRY(RTC_WAKE),
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};
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