121 lines
3.1 KiB
C
121 lines
3.1 KiB
C
/*
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* Copyright (c) 2012 Travis Geiselbrecht
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files
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* (the "Software"), to deal in the Software without restriction,
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* including without limitation the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <debug.h>
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#include <arch.h>
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#include <arch/ops.h>
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#include <arch/arm.h>
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#include <platform.h>
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#include <arch/arm/cm3.h>
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#define ENABLE_CYCLE_COUNTER 1
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extern void *vectab;
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extern int _end_of_ram;
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void *_heap_end = &_end_of_ram;
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unsigned int cm3_num_irq_pri_bits;
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unsigned int cm3_irq_pri_mask;
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void arch_early_init(void)
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{
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arch_disable_ints();
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/* set the vector table base */
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SCB->VTOR = (uint32_t)&vectab;
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/* clear any pending interrupts and set all the vectors to medium priority */
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int i;
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int groups = SCnSCB->ICTR & 0xf;
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for (i = 0; i < groups; i++) {
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NVIC->ICER[i] = 0xffffffff;
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NVIC->ICPR[i] = 0xffffffff;
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NVIC->IP[i*4] = 128; /* medium priority */
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NVIC->IP[i*4+1] = 128; /* medium priority */
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NVIC->IP[i*4+2] = 128; /* medium priority */
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NVIC->IP[i*4+3] = 128; /* medium priority */
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}
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/* number of priorities */
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for (i=0; i < 7; i++) {
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__set_BASEPRI(1 << i);
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if (__get_BASEPRI() != 0)
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break;
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}
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cm3_num_irq_pri_bits = 8 - i;
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cm3_irq_pri_mask = ~((1 << i) - 1) & 0xff;
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/* leave BASEPRI at 0 */
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__set_BASEPRI(0);
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/* set priority grouping to 0 */
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NVIC_SetPriorityGrouping(0);
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/* enable certain faults */
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SCB->SHCSR |= (SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk);
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/* set the svc and pendsv priority level to pretty low */
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SCB->SHP[11-4] = cm3_lowest_priority();
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SCB->SHP[14-4] = cm3_lowest_priority();
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/* initialize the systick mechanism */
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cm3_systick_init();
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}
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void arch_init(void)
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{
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#if ENABLE_CYCLE_COUNTER
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*REG32(SCB_DEMCR) |= 0x01000000; // global trace enable
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*REG32(DWT_CYCCNT) = 0;
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*REG32(DWT_CTRL) |= 1; // enable cycle counter
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#endif
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}
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void arch_quiesce(void)
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{
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}
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void arch_idle(void)
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{
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}
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void cm3_set_irqpri(uint32_t pri)
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{
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if (pri == 0) {
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__disable_irq(); // cpsid i
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__set_BASEPRI(0);
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} else if (pri >= 256) {
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__set_BASEPRI(0);
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__enable_irq();
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} else {
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uint32_t _pri = pri & cm3_irq_pri_mask;
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if (_pri == 0)
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__set_BASEPRI(1 << (8 - cm3_num_irq_pri_bits));
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else
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__set_BASEPRI(_pri);
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__enable_irq(); // cpsid i
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}
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}
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