Travis Geiselbrecht 6f32a0f377 [arch][riscv] use newly discovered pseudo-instructions for load/stores ...

I hadn't noticed this before, but you can directly reference a global
variable in a load/store in assembly, which combines a lla + ld/sd into
a 2 instruction pair instead of 3 due to the 12 bit offset provided in
the load/store.

2024-11-27 21:53:29 -08:00

..

include/arch

[riscv] switch stimecmp/stimecmph registers to using the raw integer format

2024-06-16 22:37:10 -07:00

arch.c

[arch][riscv] read the riscv feature string out of device tree

2024-06-01 17:21:01 -07:00

asm.S

[arch][riscv][asm] use the call pseudoinstruction instead of jal

2024-11-14 19:33:46 -08:00

exceptions.c

[arch][riscv] more interrupt cause debugging strings

2022-05-29 17:55:41 -07:00

feature.c

[arch][riscv][feature] add a few more feature bits

2024-06-02 15:31:30 -07:00

fpu_asm.S

[arch][riscv] add fpu context switch support

2022-07-17 23:27:42 -07:00

linker-onesegment.ld

[arch][riscv] fix bug with gcc 10.2 & binutils 2.35 with section padding

2020-12-09 01:59:16 -08:00

linker-twosegment.ld

[arch][riscv] fix bug with gcc 10.2 & binutils 2.35 with section padding

2020-12-09 01:59:16 -08:00

mmu.cpp

[arch][riscv] read the riscv feature string out of device tree

2024-06-01 17:21:01 -07:00

mp.c

[arch][riscv] change secondary cpu bootstrap api

2024-04-07 22:32:49 -07:00

riscv_priv.h

[arch][warnings] fix -Wmissing-declarations warnings

2021-10-21 23:08:38 -07:00

rules.mk

[arch][riscv] read the riscv feature string out of device tree

2024-06-01 17:21:01 -07:00

sbi.c

[arch][riscv] add new extensions for SBI 2.0

2024-04-23 23:27:02 -07:00

spinlock.c

[arch][riscv] general riscv spinlock cleanup

2023-12-28 17:02:07 -08:00

start.S

[arch][riscv] use newly discovered pseudo-instructions for load/stores

2024-11-27 21:53:29 -08:00

thread.c

[arch][riscv] Add more defines and optimize fpu context switch

2023-02-18 16:39:45 -08:00

time.c

[arch][riscv] add SSTC extension support

2024-06-02 15:29:53 -07:00