152 lines
4.5 KiB
C
152 lines
4.5 KiB
C
/*
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* Copyright (c) 2008 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include <lk/debug.h>
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#include <lk/reg.h>
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#include <dev/uart.h>
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#include <target/debugconfig.h>
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#include <platform/or1ksim.h>
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struct uart_stat {
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addr_t base;
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uint32_t clk_freq;
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uint shift;
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};
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static struct uart_stat uart[1] = {
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{ UART1_BASE, UART1_CLOCK_FREQ, 0 },
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};
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static inline void write_uart_reg(int port, uint reg, unsigned char data) {
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*(volatile unsigned char *)(uart[port].base + (reg << uart[port].shift)) = data;
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}
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static inline unsigned char read_uart_reg(int port, uint reg) {
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return *(volatile unsigned char *)(uart[port].base + (reg << uart[port].shift));
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}
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#define UART_RHR 0
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#define UART_THR 0
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#define UART_DLL 0
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#define UART_IER 1
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#define UART_DLH 1
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#define UART_IIR 2
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#define UART_FCR 2
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#define UART_EFR 2
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#define UART_LCR 3
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#define UART_MCR 4
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#define UART_LSR 5
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#define UART_MSR 6
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#define UART_TCR 6
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#define UART_SPR 7
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#define UART_TLR 7
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#define UART_MDR1 8
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#define UART_MDR2 9
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#define UART_SFLSR 10
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#define UART_RESUME 11
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#define UART_TXFLL 10
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#define UART_TXFLH 11
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#define UART_SFREGL 12
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#define UART_SFREGH 13
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#define UART_RXFLL 12
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#define UART_RXFLH 13
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#define UART_BLR 14
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#define UART_UASR 14
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#define UART_ACREG 15
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#define UART_SCR 16
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#define UART_SSR 17
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#define UART_EBLR 18
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#define UART_MVR 19
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#define UART_SYSC 20
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#define LCR_8N1 0x03
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#define FCR_FIFO_EN 0x01 /* Fifo enable */
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#define FCR_RXSR 0x02 /* Receiver soft reset */
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#define FCR_TXSR 0x04 /* Transmitter soft reset */
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#define MCR_DTR 0x01
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#define MCR_RTS 0x02
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#define MCR_DMA_EN 0x04
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#define MCR_TX_DFR 0x08
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#define LCR_WLS_MSK 0x03 /* character length select mask */
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#define LCR_WLS_5 0x00 /* 5 bit character length */
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#define LCR_WLS_6 0x01 /* 6 bit character length */
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#define LCR_WLS_7 0x02 /* 7 bit character length */
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#define LCR_WLS_8 0x03 /* 8 bit character length */
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#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
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#define LCR_PEN 0x08 /* Parity eneble */
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#define LCR_EPS 0x10 /* Even Parity Select */
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#define LCR_STKP 0x20 /* Stick Parity */
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#define LCR_SBRK 0x40 /* Set Break */
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#define LCR_BKSE 0x80 /* Bank select enable */
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#define LSR_DR 0x01 /* Data ready */
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#define LSR_OE 0x02 /* Overrun */
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#define LSR_PE 0x04 /* Parity error */
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#define LSR_FE 0x08 /* Framing error */
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#define LSR_BI 0x10 /* Break */
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#define LSR_THRE 0x20 /* Xmit holding register empty */
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#define LSR_TEMT 0x40 /* Xmitter empty */
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#define LSR_ERR 0x80 /* Error */
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#define LCRVAL LCR_8N1 /* 8 data, 1 stop, no parity */
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#define MCRVAL (MCR_DTR | MCR_RTS) /* RTS/DTR */
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#define FCRVAL (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR) /* Clear & enable FIFOs */
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void uart_init_port(int port, uint baud) {
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/* clear the tx & rx fifo and disable */
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uint16_t baud_divisor = (uart[port].clk_freq / 16 / baud);
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write_uart_reg(port, UART_IER, 0);
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write_uart_reg(port, UART_LCR, LCR_BKSE | LCRVAL); // config mode A
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write_uart_reg(port, UART_DLL, baud_divisor & 0xff);
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write_uart_reg(port, UART_DLH, (baud_divisor >> 8) & 0xff);
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write_uart_reg(port, UART_LCR, LCRVAL); // operational mode
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write_uart_reg(port, UART_MCR, MCRVAL);
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write_uart_reg(port, UART_FCR, FCRVAL);
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}
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void uart_init_early(void) {
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uart_init_port(DEBUG_UART, 115200);
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}
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void uart_init(void) {
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}
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int uart_putc(int port, char c ) {
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while (!(read_uart_reg(port, UART_LSR) & (1<<6))) // wait for the last char to get out
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;
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write_uart_reg(port, UART_THR, c);
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return 0;
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}
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int uart_getc(int port, bool wait) { /* returns -1 if no data available */
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if (wait) {
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while (!(read_uart_reg(port, UART_LSR) & (1<<0))) // wait for data to show up in the rx fifo
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;
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} else {
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if (!(read_uart_reg(port, UART_LSR) & (1<<0)))
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return -1;
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}
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return read_uart_reg(port, UART_RHR);
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}
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void uart_flush_tx(int port) {
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while (!(read_uart_reg(port, UART_LSR) & (1<<6))) // wait for the last char to get out
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;
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}
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void uart_flush_rx(int port) {
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// empty the rx fifo
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while (read_uart_reg(port, UART_LSR) & (1<<0)) {
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volatile char c = read_uart_reg(port, UART_RHR);
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(void)c;
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}
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}
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