148 lines
4.4 KiB
ArmAsm
148 lines
4.4 KiB
ArmAsm
/*
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* Copyright (c) 2009 Corey Tabaka
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* Copyright (c) 2015 Intel Corporation
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* Copyright (c) 2016 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include <lk/asm.h>
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#include <arch/x86/descriptor.h>
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#define PHYS_LOAD_ADDRESS (MEMBASE + KERNEL_LOAD_OFFSET)
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#define PHYS_ADDR_DELTA (KERNEL_BASE + KERNEL_LOAD_OFFSET - PHYS_LOAD_ADDRESS)
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#define PHYS(x) ((x) - PHYS_ADDR_DELTA)
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.section .rodata
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.balign 8
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DATA(_gdtr_phys)
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.short _gdt_end - _gdt - 1
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.int PHYS(_gdt)
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END_DATA(_gdtr_phys)
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.balign 8
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DATA(_gdtr)
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.short _gdt_end - _gdt - 1
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#if ARCH_X86_32
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.int _gdt
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#elif ARCH_X86_64
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.quad _gdt
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#endif
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END_DATA(_gdtr)
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.data
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.balign 8
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DATA(_gdt)
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.int 0
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.int 0
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/* ring 0 descriptors */
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.set codesel_32, . - _gdt
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_code_32_gde:
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.short 0xffff /* limit 15:00 */
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.short 0x0000 /* base 15:00 */
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.byte 0x00 /* base 23:16 */
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.byte 0b10011010 /* P(1) DPL(00) S(1) 1 C(0) R(1) A(0) */
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.byte 0b11001111 /* G(1) D(1) 0 0 limit 19:16 */
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.byte 0x0 /* base 31:24 */
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.set datasel, . - _gdt
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_data_gde:
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.short 0xffff /* limit 15:00 */
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.short 0x0000 /* base 15:00 */
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.byte 0x00 /* base 23:16 */
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.byte 0b10010010 /* P(1) DPL(00) S(1) 0 E(0) W(1) A(0) */
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.byte 0b11001111 /* G(1) B(1) 0 0 limit 19:16 */
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.byte 0x0 /* base 31:24 */
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.set user_codesel_32, . - _gdt
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_user_code_32_gde:
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.short 0xffff /* limit 15:00 */
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.short 0x0000 /* base 15:00 */
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.byte 0x00 /* base 23:16 */
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.byte 0b11111010 /* P(1) DPL(11) S(1) 1 C(0) R(1) A(0) */
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.byte 0b11001111 /* G(1) D(1) 0 0 limit 19:16 */
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.byte 0x0 /* base 31:24 */
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.set user_datasel, . - _gdt
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_user_data_32_gde:
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.short 0xffff /* limit 15:00 */
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.short 0x0000 /* base 15:00 */
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.byte 0x00 /* base 23:16 */
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.byte 0b11110010 /* P(1) DPL(11) S(1) 0 E(0) W(1) A(0) */
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.byte 0b11001111 /* G(1) B(1) 0 0 limit 19:16 */
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.byte 0x0 /* base 31:24 */
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.set codesel_64, . - _gdt
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_code_64_gde:
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.short 0xffff /* limit 15:00 */
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.short 0x0000 /* base 15:00 */
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.byte 0x00 /* base 23:16 */
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.byte 0b10011010 /* P(1) DPL(00) S(1) 1 C(0) R(1) A(0) */
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.byte 0b10101111 /* G(1) D(0) L(1) AVL(0) limit 19:16 */
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.byte 0x0 /* base 31:24 */
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.set datasel_64, . - _gdt
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_data_64_gde:
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.short 0xffff /* limit 15:00 */
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.short 0x0000 /* base 15:00 */
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.byte 0x00 /* base 23:16 */
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.byte 0b10010010 /* P(1) DPL(00) S(1) 1 C(0) R(1) A(0) */
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.byte 0b11001111 /* G(1) B(1) 0 AVL(0) limit 19:16 */
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.byte 0x0 /* base 31:24 */
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.set user_codesel_64, . - _gdt
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_user_code_64_gde:
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.short 0xffff /* limit 15:00 */
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.short 0x0000 /* base 15:00 */
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.byte 0x00 /* base 23:16 */
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.byte 0b11111010 /* P(1) DPL(11) S(1) 1 C(0) R(1) A(0) */
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.byte 0b10101111 /* G(1) D(1) L(0) AVL(0) limit 19:16 */
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.byte 0x0 /* base 31:24 */
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.set user_datasel_64, . - _gdt
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_user_data_64_gde:
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.short 0xffff /* limit 15:00 */
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.short 0x0000 /* base 15:00 */
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.byte 0x00 /* base 23:16 */
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.byte 0b11110010 /* P(1) DPL(11) S(1) 0 E(0) W(1) A(0) */
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.byte 0b11001111 /* G(1) B(1) 0 0 limit 19:16 */
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.byte 0x0 /* base 31:24 */
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/* per-cpu TSS descriptor */
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_tss_gde:
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.set i, 1
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.rept SMP_MAX_CPUS
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.short 0 /* limit 15:00 */
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.short 0 /* base 15:00 */
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.byte 0 /* base 23:16 */
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.byte 0x89 /* P(1) DPL(00) S(0) TYPE(9) */
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.byte 0x80 /* G(1) D/B(0) L(0) AVL(0) limit 19:16 */
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.byte 0 /* base 31:24 */
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#if ARCH_X86_64
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/* 64-bit TSSs are 16 bytes long */
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.int 0 /* base 63:32 */
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.int 0 /* type(0) + reserved */
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#endif
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.set i, i+1
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.endr
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/* per-cpu GS descriptor for x86-32 */
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#if ARCH_X86_32
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_percpu_gde:
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.set i, 1
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.rept SMP_MAX_CPUS
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.int 0 /* filled in by C code later */
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.int 0
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.set i, i+1
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.endr
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#endif
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END_DATA(_gdt)
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DATA(_gdt_end)
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