04b88750b3
Most of the functions for this was declared in a top level lk/ include space, so go ahead and move it there. A few exceptions: - Moved spin() over to platform/time.h and platform/time.c since the function more logically belongs to platform/time.h. Any users of spin() will need to update their headers to include platform/time.h instead. - Renamed spin_cycles() to arm_cm_spin_cycles() and moved over into arm/cm.h since it is currently defined in arch/arm-m and only used for targets that implicitly are for arm-m.
114 lines
3.6 KiB
C
114 lines
3.6 KiB
C
/*
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* Copyright (c) 2015 Brian Swetland
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include <lk/debug.h>
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#include <arch/arm/cm.h>
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#include <kernel/thread.h>
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#include <platform.h>
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#include <platform/lpc43xx-clocks.h>
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void lpc43xx_debug_early_init(void);
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void lpc43xx_debug_init(void);
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uint8_t __lpc43xx_main_clock_sel;
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uint32_t __lpc43xx_main_clock_mhz;
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void platform_early_init(void) {
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#ifndef WITH_NO_CLOCK_INIT
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unsigned cfg;
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// Different boot modes will enable different sets of clocks.
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// To keep it simple, we drop back to the 12MHz internal osc,
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// power down the other clocks, and bring things back up in an
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// orderly fashion. This costs a few hundred microseconds.
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// switch CPU clock to 12MHz internal osc
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writel(readl(BASE_M4_CLK) | BASE_AUTOBLOCK, BASE_M4_CLK);
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writel(BASE_CLK_SEL(CLK_IRC) | BASE_AUTOBLOCK, BASE_M4_CLK);
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// Disable PLL1, if it was already running
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writel(PLL1_CTRL_PD, PLL1_CTRL);
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// Disable PLL0USB, if it was already running
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writel(PLL0_CTRL_PD, PLL0USB_CTRL);
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// Disable XTAL osc if it was already running
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writel(readl(XTAL_OSC_CTRL) | 1, XTAL_OSC_CTRL);
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// Disable BYPASS or HF modes:
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writel(1, XTAL_OSC_CTRL);
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// Enable, HF=0 BYPASS=0
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writel(0, XTAL_OSC_CTRL);
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// Wait
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arm_cm_spin_cycles(3000); // 250uS @ 12MHz
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// PLL1: 12MHz -> N=(/2) -> M=(x32) -> P=(/2) 96MHz
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cfg = PLL1_CTRL_NSEL_2 | PLL1_CTRL_PSEL_1 | PLL1_CTRL_MSEL(32) |
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PLL1_CTRL_CLK_SEL(CLK_XTAL) | PLL1_CTRL_AUTOBLOCK;
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writel(cfg, PLL1_CTRL);
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while (!(readl(PLL1_STAT) & PLL1_STAT_LOCK)) ;
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writel(BASE_CLK_SEL(CLK_PLL1) | BASE_AUTOBLOCK, BASE_M4_CLK);
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// when moving from < 90 MHz to > 110MHz, must spend 50uS
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// at 90-110MHz before shifting to high speeds
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arm_cm_spin_cycles(4800); // 50uS @ 96MHz
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// disable P divider 192MHz
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writel(cfg | PLL1_CTRL_DIRECT, PLL1_CTRL);
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// 12MHz -> 480MHz settings, per boot rom
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writel(0x01967FFA, PLL0USB_MDIV);
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writel(0x00302062, PLL0USB_NP_DIV);
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// Enable PLL, wait for lock
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cfg = PLL0_CTRL_CLK_SEL(CLK_XTAL) | PLL0_CTRL_DIRECTO | PLL0_CTRL_AUTOBLOCK;
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writel(cfg, PLL0USB_CTRL);
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while (!(readl(PLL0USB_STAT) & PLL0_STAT_LOCK)) ;
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// Enable clock output
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writel(cfg | PLL0_CTRL_CLKEN, PLL0USB_CTRL);
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#if 0
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// route PLL1 / 2 to CLK0 pin for verification
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writel(0x11, 0x40086C00); // CLK0 = CLK_OUT, no PU/PD
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writel(IDIV_CLK_SEL(CLK_PLL1) | IDIV_N(2), IDIVE_CTRL);
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writel(BASE_CLK_SEL(CLK_IDIVE), BASE_OUT_CLK);
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#endif
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#if 0
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// route PLL0USB / 4 to CLK0 pin for verification
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writel(0x11, 0x40086C00); // CLK0 = CLK_OUT, no PU/PD
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writel(IDIV_CLK_SEL(CLK_PLL0USB) | IDIV_N(4), IDIVA_CTRL);
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writel(BASE_CLK_SEL(CLK_IDIVA), BASE_OUT_CLK);
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#endif
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__lpc43xx_main_clock_mhz = 192000000;
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__lpc43xx_main_clock_sel = CLK_PLL1;
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#else
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__lpc43xx_main_clock_mhz = 96000000;
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__lpc43xx_main_clock_sel = CLK_IDIVC;
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#endif
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arm_cm_systick_init(__lpc43xx_main_clock_mhz);
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lpc43xx_debug_early_init();
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}
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void lpc43xx_usb_init(u32 dmabase, size_t dmasize);
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void platform_init(void) {
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lpc43xx_debug_init();
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lpc43xx_usb_init(0x20000000, 4096);
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}
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void platform_halt(platform_halt_action suggested_action,
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platform_halt_reason reason) {
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arch_disable_ints();
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if (suggested_action == HALT_ACTION_REBOOT) {
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// CORE reset
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writel(1, 0x40053100);
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} else {
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dprintf(ALWAYS, "HALT: spinning forever... (reason = %d)\n", reason);
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}
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for (;;);
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}
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