Travis Geiselbrecht dcabc6cbe5 [platform][zynq] debug uart code tweak ...

-wait until there's a slot in the fifo before writing
-let the target set the debug uart

2014-04-20 17:50:23 -07:00

..

include/target

[platform][zynq] debug uart code tweak

2014-04-20 17:50:23 -07:00

rules.mk

[platform][zynq] add quick 'n dirty support for Xilinx Zynq FPGA SoC

2014-04-19 00:46:52 -07:00