Travis Geiselbrecht 00b06a8302 [arch][riscv] change secondary cpu bootstrap api ...

Instead of setting a counter of the number of secondaries to start, have
platform or target code pass in a list of harts to start instead. This
allows for there to be discontinuties in the layout of the cpu harts, or
in the case of some sifive based hardware, hart 0 is otherwise offline.

2024-04-07 22:32:49 -07:00

..

include/platform

[dev][interrupt][riscv_plic] merge now 3 implementations of the same plic driver into one

2023-03-09 23:09:32 -08:00

platform_p.h

[dev][interrupt][riscv_plic] merge now 3 implementations of the same plic driver into one

2023-03-09 23:09:32 -08:00

platform.c

[arch][riscv] change secondary cpu bootstrap api

2024-04-07 22:32:49 -07:00

rules.mk

[target][visionfive2] set the time base properly

2023-03-09 23:20:18 -08:00

uart.c

WIP [target][visionfive2] Add initial support for a VisionFive 2 RISC-V board

2023-03-06 01:06:27 -08:00