445f3e4ee7
Mostly driver code in various platforms. There are still some warnings in this part of the tree in lesser-used platforms.
139 lines
3.6 KiB
C
139 lines
3.6 KiB
C
/*
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* Copyright (c) 2014 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include <lk/reg.h>
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#include <stdio.h>
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#include <lk/trace.h>
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#include <assert.h>
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#include <lib/cbuf.h>
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#include <kernel/thread.h>
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#include <dev/uart.h>
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#include <platform/interrupts.h>
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#include <platform/debug.h>
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#include <platform/zynq.h>
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#define RXBUF_SIZE 16
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static cbuf_t uart_rx_buf[NUM_UARTS];
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static inline uintptr_t uart_to_ptr(unsigned int n) { return (n == 0) ? UART0_BASE : UART1_BASE; }
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static inline uint uart_to_irq(unsigned int n) { return (n == 0) ? UART0_INT : UART1_INT; }
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#define UART_REG(base, reg) (*REG32((base) + (reg)))
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static enum handler_return uart_irq(void *arg) {
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bool resched = false;
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uint port = (uint)arg;
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uintptr_t base = uart_to_ptr(port);
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/* read interrupt status and mask */
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uint32_t isr = UART_REG(base, UART_ISR);
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isr &= UART_REG(base, UART_IMR);
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if (isr & (1<<0)) { // rxtrig
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UART_REG(base, UART_ISR) = (1<< 0);
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while ((UART_REG(base, UART_SR) & (1<<1)) == 0) { // ~rempty
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char c = UART_REG(base, UART_FIFO);
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cbuf_write_char(&uart_rx_buf[port], c, false);
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resched = true;
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}
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}
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return resched ? INT_RESCHEDULE : INT_NO_RESCHEDULE;
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}
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void uart_init(void) {
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for (uint i = 0; i < NUM_UARTS; i++) {
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cbuf_initialize(&uart_rx_buf[i], RXBUF_SIZE);
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uintptr_t base = uart_to_ptr(i);
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// clear all irqs
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UART_REG(base, UART_IDR) = 0xffffffff;
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// set rx fifo trigger to 1
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UART_REG(base, UART_RXWM) = 1;
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// enable the receiver
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// NOTE: must clear rxdis and set rxen in the same write
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UART_REG(base, UART_CR) = (UART_REG(base, UART_CR) & ~(1<<3)) | (1 << 2);
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// enable rx interrupt
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UART_REG(base, UART_IER) = (1<<0); // rxtrig
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// set up interrupt handler
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register_int_handler(uart_to_irq(i), &uart_irq, (void *)i);
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unmask_interrupt(uart_to_irq(i));
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}
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}
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void uart_init_early(void) {
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for (uint i = 0; i < NUM_UARTS; i++) {
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uintptr_t base = uart_to_ptr(i);
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UART_REG(base, UART_BAUD_DIV) = UART_BRD_DIV(6);
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UART_REG(base, UART_BAUDGEN) = UART_BRG_DIV(0x3E);
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// reset the tx/rx path
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UART_REG(base, UART_CR) |= UART_CR_TXRES | UART_CR_RXRES;
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while ((UART_REG(base, UART_CR) & (UART_CR_TXRES | UART_CR_RXRES)) != 0)
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;
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// n81, clock select ref_clk
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UART_REG(base, UART_MR) = UART_MR_PAR(0x4); // no parity
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// no flow
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UART_REG(base, UART_MODEMCR) = 0;
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UART_REG(base, UART_CR) = UART_CR_TXEN;
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}
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/* Configuration for the serial console */
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/*UART_REG(UART1_BASE, UART_CR) = 0x00000017;*/
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/*UART_REG(UART1_BASE, UART_MR) = 0x00000020;*/
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}
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int uart_putc(int port, char c) {
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DEBUG_ASSERT(port >= 0 && port < NUM_UARTS);
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uintptr_t base = uart_to_ptr(port);
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/* spin while fifo is full */
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while (UART_REG(base, UART_SR) & (1<<4))
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;
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UART_REG(base, UART_FIFO) = c;
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return 1;
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}
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int uart_getc(int port, bool wait) {
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DEBUG_ASSERT(port >= 0 && port < NUM_UARTS);
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char c;
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if (cbuf_read_char(&uart_rx_buf[port], &c, wait) == 1)
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return c;
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return -1;
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}
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void uart_flush_tx(int port) {
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DEBUG_ASSERT(port >= 0 && port < NUM_UARTS);
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}
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void uart_flush_rx(int port) {
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DEBUG_ASSERT(port >= 0 && port < NUM_UARTS);
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}
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void uart_init_port(int port, uint baud) {
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DEBUG_ASSERT(port >= 0 && port < NUM_UARTS);
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PANIC_UNIMPLEMENTED;
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}
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