111 lines
3.3 KiB
C
111 lines
3.3 KiB
C
/*
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* Copyright (c) 2014 Brian Swetland
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include <platform/fpga.h>
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#include <lk/trace.h>
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#include <lk/reg.h>
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#include <lk/err.h>
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#include <platform.h>
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#include <kernel/thread.h>
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#define LOCAL_TRACE 0
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#define FPGA_TIMEOUT 1000
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#define DEVCFG_CTRL 0xF8007000
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#define PCFG_PROG_B (1 << 30)
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#define PCFG_POR_CNT_4K (1 << 29)
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#define PCAP_PR (1 << 27) // 0 = ICAP CFG, 1 = PCAP CFG
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#define PCAP_MODE (1 << 26) // 1 = Enable PCAP Interface
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#define DEVCFG_LOCK 0xF8007004
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#define DEVCFG_CFG 0xF8007008
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#define DEVCFG_INT_STS 0xF800700C
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#define DMA_DONE_INT (1 << 13)
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#define PSS_CFG_RESET_B (1 << 5) // 1 = PL in reset state
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#define PCFG_DONE_INT (1 << 2) // 1 = PL successfully programmed
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#define PCFG_INIT_PE_INT (1 << 1)
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#define PCFG_INIT_NE_INT (1 << 0)
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#define DEVCFG_INT_MASK 0xF8007010
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#define DEVCFG_STATUS 0xF8007014
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#define PCFG_INIT (1 << 4) // 1 = ready for bitstream
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#define DEVCFG_DMA_SRC_ADDR 0xF8007018
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#define DEVCFG_DMA_DST_ADDR 0xF800701C
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#define DEVCFG_DMA_SRC_LEN 0xF8007020 // words
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#define DEVCFG_DMA_DST_LEN 0xF8007024 // words
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#define DEVCFG_SW_ID 0xF8007030
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#define DEVCFG_MCTRL 0xF8007080
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#define PCFG_POR_B (1 << 8) // 1 = PL is powered on
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#define INT_PCAP_LPBK (1 << 4) // 1 = Loopback Enabled
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// Per Zynq TRM, 6.4.4
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// 1. wait for PCFG_INIT==1
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// 2. disable loopback
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// 3. set DEVCFG CTRL PCAP_PR and PCAP_MODE
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// 4. set dma src, dst, srclen, dstlen (in that specific order)
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// 5. wait for PCFG_DONE_INT==1
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status_t zynq_program_fpga(paddr_t physaddr, size_t length) {
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LTRACEF("phys 0x%lx, len 0x%zx\n", physaddr, length);
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lk_bigtime_t bt = current_time_hires();
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/* length is in words */
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length /= 4;
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lk_time_t t;
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t = current_time();
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while (!(readl(DEVCFG_STATUS) & PCFG_INIT)) {
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if (current_time() - t > FPGA_TIMEOUT) {
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TRACEF("timeout waiting for PCFG_INIT\n");
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return ERR_TIMED_OUT;
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}
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}
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writel(readl(DEVCFG_MCTRL) & (~INT_PCAP_LPBK), DEVCFG_MCTRL);
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writel(readl(DEVCFG_CTRL) | PCAP_PR | PCAP_MODE, DEVCFG_CTRL);
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writel(0xffffffff, DEVCFG_INT_STS);
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writel(physaddr, DEVCFG_DMA_SRC_ADDR);
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writel(0xFFFFFFFF, DEVCFG_DMA_DST_ADDR);
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writel(length, DEVCFG_DMA_SRC_LEN);
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writel(length, DEVCFG_DMA_DST_LEN);
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t = current_time();
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uint32_t sts = 0;
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for (;;) {
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sts = readl(DEVCFG_INT_STS);
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#if LOCAL_TRACE
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static uint32_t last = 0;
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if (last != sts) {
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printf("dsts 0x%x\n", sts);
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}
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last = sts;
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#endif
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if (sts & PCFG_DONE_INT)
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break;
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if (current_time() - t > FPGA_TIMEOUT) {
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TRACEF("timeout waiting for PCFG_DONE_INT, DEVCFG_INT_STS is 0x%x\n", sts);
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return ERR_TIMED_OUT;
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}
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}
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bt = current_time_hires() - bt;
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LTRACEF("fpga program took %llu usecs\n", bt);
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return NO_ERROR;
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}
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bool zync_fpga_config_done(void) {
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return (0 != (readl(DEVCFG_INT_STS) & PCFG_DONE_INT));
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}
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void zynq_reset_fpga(void) {
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writel(readl(DEVCFG_CTRL) & (~PCFG_PROG_B), DEVCFG_CTRL);
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writel(readl(DEVCFG_CTRL) | PCFG_PROG_B, DEVCFG_CTRL);
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}
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