127 lines
3.7 KiB
C
127 lines
3.7 KiB
C
/*
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* Copyright (c) 2012 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include <lk/debug.h>
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#include <assert.h>
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#include <dev/gpio.h>
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#include <platform/gpio.h>
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#include "ti_driverlib.h"
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static void *port_to_pointer(unsigned int port) {
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switch (port) {
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default:
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case GPIO_PORT_A:
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return (void *)GPIO_PORTA_AHB_BASE;
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case GPIO_PORT_B:
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return (void *)GPIO_PORTB_AHB_BASE;
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case GPIO_PORT_C:
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return (void *)GPIO_PORTC_AHB_BASE;
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case GPIO_PORT_D:
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return (void *)GPIO_PORTD_AHB_BASE;
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case GPIO_PORT_E:
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return (void *)GPIO_PORTE_AHB_BASE;
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case GPIO_PORT_F:
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return (void *)GPIO_PORTF_AHB_BASE;
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case GPIO_PORT_G:
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return (void *)GPIO_PORTG_AHB_BASE;
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case GPIO_PORT_H:
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return (void *)GPIO_PORTH_AHB_BASE;
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case GPIO_PORT_J:
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return (void *)GPIO_PORTJ_BASE;
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case GPIO_PORT_K:
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return (void *)GPIO_PORTK_BASE;
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case GPIO_PORT_L:
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return (void *)GPIO_PORTL_BASE;
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case GPIO_PORT_M:
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return (void *)GPIO_PORTM_BASE;
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case GPIO_PORT_N:
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return (void *)GPIO_PORTN_BASE;
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case GPIO_PORT_P:
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return (void *)GPIO_PORTP_BASE;
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case GPIO_PORT_Q:
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return (void *)GPIO_PORTQ_BASE;
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}
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}
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void stellaris_gpio_early_init(void) {
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/* Disable hitting the AHB bits on this target, which
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* is probably qemu emulated. QEMU does not implement
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* these registers and will crash.
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*/
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#if !TARGET_LM3S6965EVB
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SysCtlGPIOAHBEnable(SYSCTL_PERIPH_GPIOA);
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SysCtlGPIOAHBEnable(SYSCTL_PERIPH_GPIOB);
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SysCtlGPIOAHBEnable(SYSCTL_PERIPH_GPIOC);
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SysCtlGPIOAHBEnable(SYSCTL_PERIPH_GPIOD);
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SysCtlGPIOAHBEnable(SYSCTL_PERIPH_GPIOE);
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SysCtlGPIOAHBEnable(SYSCTL_PERIPH_GPIOF);
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SysCtlGPIOAHBEnable(SYSCTL_PERIPH_GPIOG);
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SysCtlGPIOAHBEnable(SYSCTL_PERIPH_GPIOH);
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#endif
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SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ);
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}
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void stellaris_gpio_init(void) {
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}
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#if 0
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int gpio_config(unsigned nr, unsigned flags) {
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uint port = GPIO_PORT(nr);
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uint pin = GPIO_PIN(nr);
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enable_port(port);
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GPIO_InitTypeDef init;
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init.GPIO_Speed = GPIO_Speed_50MHz;
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init.GPIO_Pin = (1 << pin);
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if (flags & GPIO_STM32_AF) {
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if (flags & GPIO_STM32_OD)
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init.GPIO_Mode = GPIO_Mode_Out_OD;
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else
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init.GPIO_Mode = GPIO_Mode_AF_PP;
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} else if (flags & GPIO_OUTPUT) {
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if (flags & GPIO_STM32_OD)
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init.GPIO_Mode = GPIO_Mode_Out_OD;
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else
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init.GPIO_Mode = GPIO_Mode_Out_PP;
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} else { // GPIO_INPUT
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if (flags & GPIO_PULLUP) {
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init.GPIO_Mode = GPIO_Mode_IPU;
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} else if (flags & GPIO_PULLDOWN) {
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init.GPIO_Mode = GPIO_Mode_IPD;
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} else {
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init.GPIO_Mode = GPIO_Mode_IN_FLOATING;
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}
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}
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GPIO_Init(port_to_pointer(port), &init);
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return 0;
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}
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#endif
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void gpio_set(unsigned nr, unsigned on) {
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GPIOPinWrite((unsigned int)port_to_pointer(GPIO_PORT(nr)), 1 << GPIO_PIN(nr), on ? (1 << GPIO_PIN(nr)) : 0);
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}
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int gpio_get(unsigned nr) {
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return GPIOPinRead((unsigned int)port_to_pointer(GPIO_PORT(nr)), 1 << GPIO_PIN(nr));
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}
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