c3ea652c1f
The IRQ calculation for the virtio range was off by 8, which caused the virtio code to override the interrupt registration for the RTC, which caused it to stop firing. Clean up the #defines that define irq mappings to fix this issue.
131 lines
3.1 KiB
C
131 lines
3.1 KiB
C
/*
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* Copyright (c) 2021 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include "platform_p.h"
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#include <assert.h>
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#include <inttypes.h>
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#include <lk/err.h>
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#include <lk/debug.h>
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#include <lk/reg.h>
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#include <lk/trace.h>
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#include <kernel/debug.h>
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#include <kernel/thread.h>
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#include <platform/interrupts.h>
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#include <platform/virt.h>
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#include <platform/timer.h>
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#include <platform.h>
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#define LOCAL_TRACE 0
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// implementation of RTC at
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// https://github.com/qemu/qemu/blob/master/hw/rtc/goldfish_rtc.c
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volatile uint32_t * const goldfish_rtc_base = (void *)VIRT_GF_RTC_MMIO_BASE;
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// registers
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enum {
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RTC_TIME_LOW = 0x00,
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RTC_TIME_HIGH = 0x04,
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RTC_ALARM_LOW = 0x08,
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RTC_ALARM_HIGH = 0x0c,
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RTC_IRQ_ENABLED = 0x10,
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RTC_CLEAR_ALARM = 0x14,
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RTC_ALARM_STATUS = 0x18,
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RTC_CLEAR_INTERRUPT = 0x1c,
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};
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static uint64_t system_boot_offset;
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static platform_timer_callback t_callback;
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static void *t_arg;
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static void write_reg(unsigned int reg, uint32_t val) {
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goldfish_rtc_base[reg / 4] = val;
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}
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static uint32_t read_reg(unsigned int reg) {
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return goldfish_rtc_base[reg / 4];
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}
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// raw time from the RTC is ns wall time
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static uint64_t read_raw_time(void) {
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uint32_t low, high;
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// read both registers and assemble a 64bit counter
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// reading low first latches a shadow high register which will prevent wraparound
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low = read_reg(RTC_TIME_LOW);
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high = read_reg(RTC_TIME_HIGH);
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return ((uint64_t)high << 32) | low;
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}
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enum handler_return rtc_irq(void *unused) {
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enum handler_return ret = INT_NO_RESCHEDULE;
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write_reg(RTC_CLEAR_ALARM, 1);
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write_reg(RTC_CLEAR_INTERRUPT, 1);
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if (t_callback) {
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ret = t_callback(t_arg, current_time());
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}
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return ret;
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}
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void goldfish_rtc_early_init(void) {
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// sample the timer and use it as a offset for system start
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system_boot_offset = read_raw_time();
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// clear and stop any pending irqs on the timer
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platform_stop_timer();
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register_int_handler(VIRT_GF_RTC_IRQ_BASE, &rtc_irq, NULL);
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unmask_interrupt(VIRT_GF_RTC_IRQ_BASE);
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// its okay to enable the irq since we've cleared the alarm and any pending interrupts
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write_reg(RTC_IRQ_ENABLED, 1);
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}
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void goldfish_rtc_init(void) {
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}
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lk_bigtime_t current_time_hires(void) {
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uint64_t t = read_raw_time() - system_boot_offset;
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return t / 1000ULL; // ns -> us
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}
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lk_time_t current_time(void) {
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uint64_t t = read_raw_time() - system_boot_offset;
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return (lk_time_t)(t / 1000000ULL); // ns -> ms
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}
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status_t platform_set_oneshot_timer (platform_timer_callback callback, void *arg, lk_time_t interval) {
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LTRACEF("callback %p, arg %p, interval %u\n", callback, arg, interval);
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t_callback = callback;
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t_arg = arg;
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uint64_t delta = read_raw_time();
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delta += interval * 1000000ULL;
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write_reg(RTC_ALARM_HIGH, delta >> 32);
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write_reg(RTC_ALARM_LOW, delta & 0xffffffff);
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return NO_ERROR;
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}
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void platform_stop_timer(void) {
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LTRACE;
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write_reg(RTC_CLEAR_ALARM, 1);
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write_reg(RTC_CLEAR_INTERRUPT, 1);
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}
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