261 lines
7.1 KiB
C
261 lines
7.1 KiB
C
/*
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* Copyright (c) 2009 Corey Tabaka
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* Copyright (c) 2015 Intel Corporation
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include <sys/types.h>
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#include <lk/debug.h>
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#include <lk/trace.h>
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#include <lk/err.h>
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#include <lk/reg.h>
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#include <kernel/thread.h>
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#include <platform/interrupts.h>
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#include <arch/ops.h>
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#include <arch/mips.h>
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#include <platform/qemu-mips.h>
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#define LOCAL_TRACE 0
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static spin_lock_t lock;
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#define PIC1 0x20
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#define PIC2 0xA0
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#define ICW1 0x11
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#define ICW4 0x01
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#define PIC1_CMD 0x20
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#define PIC1_DATA 0x21
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#define PIC2_CMD 0xA0
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#define PIC2_DATA 0xA1
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#define PIC_READ_IRR 0x0a /* OCW3 irq ready next CMD read */
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#define PIC_READ_ISR 0x0b /* OCW3 irq service next CMD read */
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#define ICW1_ICW4 0x01 /* ICW4 (not) needed */
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#define ICW1_SINGLE 0x02 /* Single (cascade) mode */
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#define ICW1_INTERVAL4 0x04 /* Call address interval 4 (8) */
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#define ICW1_LEVEL 0x08 /* Level triggered (edge) mode */
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#define ICW1_INIT 0x10 /* Initialization */
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#define ICW4_8086 0x01 /* 8086/88 (MCS-80/85) mode */
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#define ICW4_AUTO 0x02 /* Auto (normal) EOI */
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#define ICW4_BUF_SLAVE 0x08 /* Buffered mode/slave */
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#define ICW4_BUF_MASTER 0x0C /* Buffered mode/master */
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#define ICW4_SFNM 0x10 /* Special fully nested (not) */
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struct int_handler_struct {
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int_handler handler;
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void *arg;
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};
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#define INT_PIC2 2
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static struct int_handler_struct int_handler_table[INT_VECTORS];
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/*
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* Cached IRQ mask (enabled/disabled)
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*/
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static uint8_t irqMask[2];
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/*
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* init the PICs and remap them
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*/
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static void map(uint32_t pic1, uint32_t pic2) {
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/* send ICW1 */
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isa_write_8(PIC1, ICW1);
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isa_write_8(PIC2, ICW1);
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/* send ICW2 */
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isa_write_8(PIC1 + 1, pic1); /* remap */
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isa_write_8(PIC2 + 1, pic2); /* pics */
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/* send ICW3 */
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isa_write_8(PIC1 + 1, 4); /* IRQ2 -> connection to slave */
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isa_write_8(PIC2 + 1, 2);
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/* send ICW4 */
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isa_write_8(PIC1 + 1, 2|5);
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isa_write_8(PIC2 + 1, 2|1);
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/* disable all IRQs */
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isa_write_8(PIC1 + 1, 0xff);
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isa_write_8(PIC2 + 1, 0xff);
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irqMask[0] = 0xff;
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irqMask[1] = 0xff;
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}
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static void enable(unsigned int vector, bool enable) {
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if (vector < 8) {
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uint8_t bit = 1 << vector;
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if (enable && (irqMask[0] & bit)) {
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irqMask[0] = isa_read_8(PIC1 + 1);
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irqMask[0] &= ~bit;
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isa_write_8(PIC1 + 1, irqMask[0]);
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irqMask[0] = isa_read_8(PIC1 + 1);
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} else if (!enable && !(irqMask[0] & bit)) {
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irqMask[0] = isa_read_8(PIC1 + 1);
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irqMask[0] |= bit;
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isa_write_8(PIC1 + 1, irqMask[0]);
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irqMask[0] = isa_read_8(PIC1 + 1);
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}
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} else if (vector < 16) {
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vector -= 8;
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uint8_t bit = 1 << vector;
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if (enable && (irqMask[1] & bit)) {
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irqMask[1] = isa_read_8(PIC2 + 1);
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irqMask[1] &= ~bit;
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isa_write_8(PIC2 + 1, irqMask[1]);
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irqMask[1] = isa_read_8(PIC2 + 1);
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} else if (!enable && !(irqMask[1] & bit)) {
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irqMask[1] = isa_read_8(PIC2 + 1);
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irqMask[1] |= bit;
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isa_write_8(PIC2 + 1, irqMask[1]);
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irqMask[1] = isa_read_8(PIC2 + 1);
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}
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bit = 1 << INT_PIC2;
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if (irqMask[1] != 0xff && (irqMask[0] & bit)) {
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irqMask[0] = isa_read_8(PIC1 + 1);
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irqMask[0] &= ~bit;
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isa_write_8(PIC1 + 1, irqMask[0]);
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irqMask[0] = isa_read_8(PIC1 + 1);
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} else if (irqMask[1] == 0 && !(irqMask[0] & bit)) {
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irqMask[0] = isa_read_8(PIC1 + 1);
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irqMask[0] |= bit;
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isa_write_8(PIC1 + 1, irqMask[0]);
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irqMask[0] = isa_read_8(PIC1 + 1);
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}
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}
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}
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static void issueEOI(unsigned int vector) {
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if (vector < 8) {
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isa_write_8(PIC1, 0x20);
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} else if (vector < 16) {
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isa_write_8(PIC2, 0x20);
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isa_write_8(PIC1, 0x20); // must issue both for the second PIC
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}
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}
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/* Helper func */
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static uint16_t __pic_get_irq_reg(uint ocw3) {
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/* OCW3 to PIC CMD to get the register values. PIC2 is chained, and
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* represents IRQs 8-15. PIC1 is IRQs 0-7, with 2 being the chain */
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isa_write_8(PIC1_CMD, ocw3);
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isa_write_8(PIC2_CMD, ocw3);
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return (isa_read_8(PIC2_CMD) << 8) | isa_read_8(PIC1_CMD);
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}
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/* Returns the combined value of the cascaded PICs irq request register */
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static uint16_t pic_get_irr(void) {
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return __pic_get_irq_reg(PIC_READ_IRR);
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}
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/* Returns the combined value of the cascaded PICs in-service register */
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static uint16_t pic_get_isr(void) {
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return __pic_get_irq_reg(PIC_READ_ISR);
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}
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void platform_init_interrupts(void) {
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// rebase the PIC out of the way of processor exceptions
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map(0, 8);
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}
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status_t mask_interrupt(unsigned int vector) {
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if (vector >= INT_VECTORS)
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return ERR_INVALID_ARGS;
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LTRACEF("vector %d\n", vector);
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spin_lock_saved_state_t state;
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spin_lock_irqsave(&lock, state);
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enable(vector, false);
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spin_unlock_irqrestore(&lock, state);
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return NO_ERROR;
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}
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void platform_mask_irqs(void) {
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irqMask[0] = isa_read_8(PIC1 + 1);
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irqMask[1] = isa_read_8(PIC2 + 1);
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isa_write_8(PIC1 + 1, 0xff);
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isa_write_8(PIC2 + 1, 0xff);
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irqMask[0] = isa_read_8(PIC1 + 1);
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irqMask[1] = isa_read_8(PIC2 + 1);
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}
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status_t unmask_interrupt(unsigned int vector) {
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if (vector >= INT_VECTORS)
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return ERR_INVALID_ARGS;
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LTRACEF("vector %d\n", vector);
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spin_lock_saved_state_t state;
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spin_lock_irqsave(&lock, state);
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enable(vector, true);
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spin_unlock_irqrestore(&lock, state);
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return NO_ERROR;
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}
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enum handler_return platform_irq(struct mips_iframe *iframe, uint vector) {
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// figure out which irq is pending
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// issue OCW3 poll commands to PIC1 and (potentially) PIC2
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isa_write_8(PIC1_CMD, (1<<3) | (1<<2));
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uint8_t val = isa_read_8(PIC1_CMD);
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if ((val & 0x80) == 0) {
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// spurious?
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return INT_NO_RESCHEDULE;
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}
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val &= ~0x80;
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if (val == INT_PIC2) {
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isa_write_8(PIC2_CMD, (1<<3) | (1<<2));
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val = isa_read_8(PIC2_CMD);
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if ((val & 0x80) == 0) {
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// spurious?
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return INT_NO_RESCHEDULE;
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}
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val &= ~0x80;
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}
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vector = val;
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LTRACEF("poll vector 0x%x\n", vector);
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THREAD_STATS_INC(interrupts);
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// deliver the interrupt
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enum handler_return ret = INT_NO_RESCHEDULE;
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if (int_handler_table[vector].handler)
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ret = int_handler_table[vector].handler(int_handler_table[vector].arg);
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return ret;
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}
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void register_int_handler(unsigned int vector, int_handler handler, void *arg) {
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if (vector >= INT_VECTORS)
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panic("register_int_handler: vector out of range %d\n", vector);
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spin_lock_saved_state_t state;
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spin_lock_irqsave(&lock, state);
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int_handler_table[vector].arg = arg;
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int_handler_table[vector].handler = handler;
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spin_unlock_irqrestore(&lock, state);
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}
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