fb1e414a09
-Add a bus manager level, which is an object oriented walk of the pci busses to build a per device object for later manipulation. -Add features to enable MSI interrupts. -Extend generic interrupt api to allow the platform to allocate vectors for MSI interrupts. -Rearrange a bit of the pc platform for the platform api changes. -Add PC platform support for using the local apic to EOI MSI vectors. -Fix up a few existing PCI drivers for small API changes. -Add a few stubbed out routines for non PC platforms that use PCI.
139 lines
3.5 KiB
C
139 lines
3.5 KiB
C
/*
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* Copyright (c) 2009 Corey Tabaka
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* Copyright (c) 2015 Intel Corporation
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include <sys/types.h>
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#include <lk/debug.h>
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#include <lk/err.h>
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#include <lk/reg.h>
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#include <lk/trace.h>
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#include <assert.h>
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#include <kernel/thread.h>
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#include <platform/interrupts.h>
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#include <arch/ops.h>
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#include <arch/x86.h>
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#include <kernel/spinlock.h>
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#include "platform_p.h"
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#include <platform/pc.h>
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#define LOCAL_TRACE 1
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/* PIC information */
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/*
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* Cached IRQ mask (enabled/disabled)
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*/
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static uint8_t irqMask[2];
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#define PIC1 0x20
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#define PIC2 0xA0
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#define ICW1 0x11
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#define ICW4 0x01
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/*
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* init the PICs and remap them
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*/
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static void map(uint32_t pic1, uint32_t pic2) {
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/* send ICW1 */
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outp(PIC1, ICW1);
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outp(PIC2, ICW1);
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/* send ICW2 */
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outp(PIC1 + 1, pic1); /* remap */
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outp(PIC2 + 1, pic2); /* pics */
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/* send ICW3 */
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outp(PIC1 + 1, 4); /* IRQ2 -> connection to slave */
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outp(PIC2 + 1, 2);
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/* send ICW4 */
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outp(PIC1 + 1, 5);
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outp(PIC2 + 1, 1);
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/* disable all IRQs */
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outp(PIC1 + 1, 0xff);
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outp(PIC2 + 1, 0xff);
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irqMask[0] = 0xff;
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irqMask[1] = 0xff;
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}
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void pic_init(void) {
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// rebase the PIC out of the way of processor exceptions
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map(INT_PIC1_BASE, INT_PIC2_BASE);
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}
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void pic_enable(unsigned int vector, bool enable) {
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if (vector >= INT_PIC1_BASE && vector < INT_PIC1_BASE + 8) {
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vector -= INT_PIC1_BASE;
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uint8_t bit = 1 << vector;
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if (enable && (irqMask[0] & bit)) {
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irqMask[0] = inp(PIC1 + 1);
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irqMask[0] &= ~bit;
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outp(PIC1 + 1, irqMask[0]);
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irqMask[0] = inp(PIC1 + 1);
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} else if (!enable && !(irqMask[0] & bit)) {
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irqMask[0] = inp(PIC1 + 1);
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irqMask[0] |= bit;
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outp(PIC1 + 1, irqMask[0]);
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irqMask[0] = inp(PIC1 + 1);
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}
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} else if (vector >= INT_PIC2_BASE && vector < INT_PIC2_BASE + 8) {
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vector -= INT_PIC2_BASE;
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uint8_t bit = 1 << vector;
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if (enable && (irqMask[1] & bit)) {
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irqMask[1] = inp(PIC2 + 1);
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irqMask[1] &= ~bit;
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outp(PIC2 + 1, irqMask[1]);
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irqMask[1] = inp(PIC2 + 1);
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} else if (!enable && !(irqMask[1] & bit)) {
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irqMask[1] = inp(PIC2 + 1);
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irqMask[1] |= bit;
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outp(PIC2 + 1, irqMask[1]);
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irqMask[1] = inp(PIC2 + 1);
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}
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bit = 1 << (INT_PIC2 - INT_PIC1_BASE);
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if (irqMask[1] != 0xff && (irqMask[0] & bit)) {
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irqMask[0] = inp(PIC1 + 1);
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irqMask[0] &= ~bit;
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outp(PIC1 + 1, irqMask[0]);
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irqMask[0] = inp(PIC1 + 1);
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} else if (irqMask[1] == 0 && !(irqMask[0] & bit)) {
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irqMask[0] = inp(PIC1 + 1);
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irqMask[0] |= bit;
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outp(PIC1 + 1, irqMask[0]);
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irqMask[0] = inp(PIC1 + 1);
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}
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}
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}
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void pic_eoi(unsigned int vector) {
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if (vector >= INT_PIC1_BASE && vector <= INT_PIC1_BASE + 7) {
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outp(PIC1, 0x20);
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} else if (vector >= INT_PIC2_BASE && vector <= INT_PIC2_BASE + 7) {
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outp(PIC2, 0x20);
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outp(PIC1, 0x20); // must issue both for the second PIC
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}
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}
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void pic_mask_interrupts(void) {
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irqMask[0] = inp(PIC1 + 1);
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irqMask[1] = inp(PIC2 + 1);
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outp(PIC1 + 1, 0xff);
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outp(PIC2 + 1, 0xff);
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irqMask[0] = inp(PIC1 + 1);
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irqMask[1] = inp(PIC2 + 1);
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}
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