71e795de19
- Added very basic user page table support (needed to bootstrap the secondary cpus) - Added MP bootup code for 32bit.
200 lines
4.4 KiB
ArmAsm
200 lines
4.4 KiB
ArmAsm
#include <lk/asm.h>
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#include <arch/x86/descriptor.h>
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#if WITH_SMP
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#define LOAD_ADDRESS 0x4000
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#define MSR_EFER 0xc0000080
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#define EFER_LME 0x00000100
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#define ARGS_ADDRESS (LOAD_ADDRESS + 0x1000)
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#define ARGS_CR3 (ARGS_ADDRESS + 0x00)
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#if ARCH_X86_64
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#define ARGS_STACK (ARGS_ADDRESS + 0x08)
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#else
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#define ARGS_STACK (ARGS_ADDRESS + 0x04)
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#endif
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.text
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.code16
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// secondary cpu boot entry point and switch to protected mode
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// enters with the following state:
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// real mode, CS 0x0400, PC 0 (physical address 0x4000)
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// LOAD_ADDRESS (physical) == mp_boot_start (virtual)
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FUNCTION(mp_boot_start)
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// jump over the temp GDT below and switch to a flat memory segment (0)
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ljmp $0, $(LOAD_ADDRESS + (.Lafter_gdt - mp_boot_start))
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.org 0x8
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.Lgdt:
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// stuff the GDTR in the first entry
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.short (8*4)
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.int (LOAD_ADDRESS + 0x8) // address of .Lgdt
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.short 0
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// 0x8 code flat 32bit
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.short 0xffff /* limit 15:00 */
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.short 0x0000 /* base 15:00 */
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.byte 0x00 /* base 23:16 */
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.byte 0b10011010 /* P(1) DPL(00) S(1) 1 C(0) R(1) A(0) */
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.byte 0b11001111 /* G(1) D(1) 0 0 limit 19:16 */
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.byte 0x0 /* base 31:24 */
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// 0x10 data flat 32bit
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.short 0xffff /* limit 15:00 */
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.short 0x0000 /* base 15:00 */
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.byte 0x00 /* base 23:16 */
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.byte 0b10010010 /* P(1) DPL(00) S(1) 0 E(0) W(1) A(0) */
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.byte 0b11001111 /* G(1) B(1) 0 0 limit 19:16 */
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.byte 0x0 /* base 31:24 */
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// 0x18 code 64bit
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.short 0xffff /* limit 15:00 */
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.short 0x0000 /* base 15:00 */
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.byte 0x00 /* base 23:16 */
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.byte 0b10011010 /* P(1) DPL(00) S(1) 1 C(0) R(1) A(0) */
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.byte 0b10101111 /* G(1) D(0) L(1) AVL(0) limit 19:16 */
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.byte 0x0 /* base 31:24 */
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.Lafter_gdt:
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// load the above GDT
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lgdt (LOAD_ADDRESS + 0x08)
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// switch to protected mode
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movl %cr0, %eax
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orl $1, %eax
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movl %eax, %cr0
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// jump to 32bit mode
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ljmpl $0x8, $(LOAD_ADDRESS + (.Lprot - mp_boot_start))
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.Lprot:
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.code32
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// we're now in 32bit mode, set up the 32bit data segment registers
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mov $0x10, %ax
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mov %ax, %ss
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mov %ax, %ds
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mov %ax, %es
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mov %ax, %fs
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mov %ax, %gs
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#if ARCH_X86_64
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// set up 64bit paging
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// set PAE bit in CR4
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mov %cr4, %eax
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or $(1<<5), %eax
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mov %eax, %cr4
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// Enable Long mode
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movl $MSR_EFER ,%ecx
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rdmsr
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orl $EFER_LME,%eax
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wrmsr
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// load trampoline page table
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movl (ARGS_CR3), %eax
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mov %eax, %cr3
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// enable paging, now we're in 32bit compatibility mode
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mov %cr0, %eax
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btsl $(31), %eax
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mov %eax, %cr0
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// load a very temporary stack pointer
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movl $(LOAD_ADDRESS + 0x800), %esp
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// Use a far jump to get into 64bit mode
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pushl $0x18
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pushl $(LOAD_ADDRESS + (.Lfarjump64 - mp_boot_start))
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lret
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.code64
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.Lfarjump64:
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/* branch to our high address */
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movq (.Lhigh_addr), %rax
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jmp *%rax
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.Lhigh_addr:
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.quad mp_boot_start_high
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#else // ARCH_X86_32
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// set up 32bit paging
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// set PSE bit in CR4
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mov %cr4, %eax
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or $(1<<4), %eax
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mov %eax, %cr4
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// load trampoline page table
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movl (ARGS_CR3), %eax
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mov %eax, %cr3
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// enable paging
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mov %cr0, %eax
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btsl $(31), %eax
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mov %eax, %cr0
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// Branch to the high address
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lea mp_boot_start_high, %eax
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jmp *%eax
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#endif
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DATA(mp_boot_end)
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END_FUNCTION(mp_boot_start)
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FUNCTION(mp_boot_start_high)
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#if ARCH_X86_64
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// set up stack pointer
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mov (ARGS_STACK), %rsp
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// load the real GDT
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lgdt _gdtr
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push $CODE_64_SELECTOR
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lea .Lnext(%rip), %rax
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push %rax
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lretq
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.Lnext:
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// zero out the segment registers
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xor %ax, %ax
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mov %ax, %ds
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mov %ax, %es
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mov %ax, %fs
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mov %ax, %gs
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mov %ax, %ss
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// call into C
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cld
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mov $ARGS_ADDRESS, %rdi
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call secondary_entry
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jmp .
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#else // ARCH_X86_32
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// set up stack pointer
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mov (ARGS_STACK), %esp
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// load the real GDT
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lgdt _gdtr
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push $CODE_SELECTOR
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lea .Lnext, %eax
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push %eax
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lret
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.Lnext:
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// Load the real segment registers
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mov $DATA_SELECTOR, %ax
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mov %ax, %ds
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mov %ax, %es
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mov %ax, %fs
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mov %ax, %gs
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mov %ax, %ss
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// call into C
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cld
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push $ARGS_ADDRESS
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call secondary_entry
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jmp .
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#endif
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END_FUNCTION(mp_boot_start_high)
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#endif // WITH_SMP |