d8fa82cb91
Almost nothing changes here except moving braces to the same line as the function declaration. Everything else is largely whitespace changes and a few dangling files with tab indents. See scripts/codestyle
309 lines
9.4 KiB
C
309 lines
9.4 KiB
C
/*
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* Copyright (c) 2008, Google Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Google, Inc. nor the names of its contributors
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* may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <arch/arm.h>
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#include <lk/reg.h>
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#include <kernel/thread.h>
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#include <platform/interrupts.h>
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#include <sync_write.h>
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#include <platform/mt_typedefs.h>
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#include <platform/mt_reg_base.h>
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#include <platform/mt_gpt.h>
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#include <platform/mt_irq.h>
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#include <lk/debug.h>
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#define GIC_ICDISER0 (GIC_DIST_BASE + 0x100)
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#define GIC_ICDISER1 (GIC_DIST_BASE + 0x104)
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#define GIC_ICDISER2 (GIC_DIST_BASE + 0x108)
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#define GIC_ICDISER3 (GIC_DIST_BASE + 0x10C)
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#define GIC_ICDISER4 (GIC_DIST_BASE + 0x110)
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#define GIC_ICDISER5 (GIC_DIST_BASE + 0x114)
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#define GIC_ICDISER6 (GIC_DIST_BASE + 0x118)
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#define GIC_ICDISER7 (GIC_DIST_BASE + 0x11C)
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#define GIC_ICDICER0 (GIC_DIST_BASE + 0x180)
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#define GIC_ICDICER1 (GIC_DIST_BASE + 0x184)
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#define GIC_ICDICER2 (GIC_DIST_BASE + 0x188)
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#define GIC_ICDICER3 (GIC_DIST_BASE + 0x18C)
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#define GIC_ICDICER4 (GIC_DIST_BASE + 0x190)
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#define GIC_ICDICER5 (GIC_DIST_BASE + 0x194)
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#define GIC_ICDICER6 (GIC_DIST_BASE + 0x198)
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#define GIC_ICDICER7 (GIC_DIST_BASE + 0x19C)
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#define INT_POL_CTL0 (MCUCFG_BASE + 0x620)
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static void mt_gic_cpu_init(void) {
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DRV_WriteReg32(GIC_CPU_BASE + GIC_CPU_PRIMASK, 0xF0);
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DRV_WriteReg32(GIC_CPU_BASE + GIC_CPU_CTRL, 0x1);
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dsb();
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}
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static void mt_gic_dist_init(void) {
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unsigned int i;
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#ifndef MTK_FORCE_CLUSTER1
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unsigned int cpumask = 1 << 0;
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#else
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unsigned int cpumask = 1 << 4;
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#endif
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cpumask |= cpumask << 8;
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cpumask |= cpumask << 16;
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DRV_WriteReg32(GIC_DIST_BASE + GIC_DIST_CTRL, 0);
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/*
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* Set all global interrupts to be level triggered, active low.
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*/
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for (i = 32; i < (MT_NR_SPI + 32); i += 16) {
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DRV_WriteReg32(GIC_DIST_BASE + GIC_DIST_CONFIG + i * 4 / 16, 0);
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}
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/*
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* Set all global interrupts to this CPU only.
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*/
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for (i = 32; i < (MT_NR_SPI + 32); i += 4) {
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DRV_WriteReg32(GIC_DIST_BASE + GIC_DIST_TARGET + i * 4 / 4, cpumask);
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}
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/*
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* Set priority on all interrupts.
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*/
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for (i = 0; i < NR_IRQ_LINE; i += 4) {
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DRV_WriteReg32(GIC_DIST_BASE + GIC_DIST_PRI + i * 4 / 4, 0xA0A0A0A0);
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}
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/*
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* Disable all interrupts.
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*/
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for (i = 0; i < NR_IRQ_LINE; i += 32) {
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DRV_WriteReg32(GIC_DIST_BASE + GIC_DIST_ENABLE_CLEAR + i * 4 / 32, 0xFFFFFFFF);
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}
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dsb();
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DRV_WriteReg32(GIC_DIST_BASE + GIC_DIST_CTRL, 1);
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}
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void platform_init_interrupts(void) {
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mt_gic_dist_init();
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mt_gic_cpu_init();
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}
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void platform_deinit_interrupts(void) {
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unsigned int irq;
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DRV_WriteReg32(GIC_ICDICER0, 0xFFFFFFFF);
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DRV_WriteReg32(GIC_ICDICER1, 0xFFFFFFFF);
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DRV_WriteReg32(GIC_ICDICER2, 0xFFFFFFFF);
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DRV_WriteReg32(GIC_ICDICER3, 0xFFFFFFFF);
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DRV_WriteReg32(GIC_ICDICER4, 0xFFFFFFFF);
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DRV_WriteReg32(GIC_ICDICER5, 0xFFFFFFFF);
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DRV_WriteReg32(GIC_ICDICER6, 0xFFFFFFFF);
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DRV_WriteReg32(GIC_ICDICER7, 0xFFFFFFFF);
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dsb();
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while ((irq = DRV_Reg32(GIC_CPU_BASE + GIC_CPU_INTACK)) != 1023 ) {
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DRV_WriteReg32(GIC_CPU_BASE + GIC_CPU_EOI, irq);
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}
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}
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extern void lk_scheduler(void);
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//extern void lk_usb_scheduler(void);
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extern void lk_nand_irq_handler(unsigned int irq);
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//extern void lk_msdc_irq_handler(unsigned int irq);
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#ifdef DUMMY_AP
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extern void dummy_ap_irq_handler(unsigned int irq);
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#endif
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enum handler_return platform_irq(struct arm_iframe *frame) {
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unsigned int irq = DRV_Reg32(GIC_CPU_BASE + GIC_CPU_INTACK);
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if (irq == MT_GPT_IRQ_ID)
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lk_scheduler();
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// else if(irq == MT_USB0_IRQ_ID)
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// lk_usb_scheduler();
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#ifndef MTK_EMMC_SUPPORT
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// else if(irq == MT_NFI_IRQ_ID)
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// lk_nand_irq_handler(irq);
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#endif
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// else if(irq == MT_MSDC0_IRQ_ID || irq == MT_MSDC1_IRQ_ID)
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// lk_msdc_irq_handler(irq);
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#ifdef DUMMY_AP
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dummy_ap_irq_handler(irq);
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#endif
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//return INT_NO_RESCHEDULE;
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return INT_RESCHEDULE;
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}
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void platform_fiq(struct arm_iframe *frame) {
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}
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void mt_irq_set_polarity(unsigned int irq, unsigned int polarity) {
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unsigned int offset;
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unsigned int reg_index;
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unsigned int value;
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// peripheral device's IRQ line is using GIC's SPI, and line ID >= GIC_PRIVATE_SIGNALS
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if (irq < GIC_PRIVATE_SIGNALS) {
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return;
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}
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offset = (irq - GIC_PRIVATE_SIGNALS) & 0x1F;
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reg_index = (irq - GIC_PRIVATE_SIGNALS) >> 5;
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if (polarity == 0) {
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value = DRV_Reg32(INT_POL_CTL0 + (reg_index * 4));
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value |= (1 << offset); // always invert the incoming IRQ's polarity
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DRV_WriteReg32((INT_POL_CTL0 + (reg_index * 4)), value);
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} else {
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value = DRV_Reg32(INT_POL_CTL0 + (reg_index * 4));
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value &= ~(0x1 << offset);
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DRV_WriteReg32(INT_POL_CTL0 + (reg_index * 4), value);
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}
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}
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void mt_irq_set_sens(unsigned int irq, unsigned int sens) {
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unsigned int config;
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if (sens == MT65xx_EDGE_SENSITIVE) {
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config = DRV_Reg32(GIC_DIST_BASE + GIC_DIST_CONFIG + (irq / 16) * 4);
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config |= (0x2 << (irq % 16) * 2);
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DRV_WriteReg32(GIC_DIST_BASE + GIC_DIST_CONFIG + (irq / 16) * 4, config);
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} else {
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config = DRV_Reg32(GIC_DIST_BASE + GIC_DIST_CONFIG + (irq / 16) * 4);
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config &= ~(0x2 << (irq % 16) * 2);
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DRV_WriteReg32( GIC_DIST_BASE + GIC_DIST_CONFIG + (irq / 16) * 4, config);
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}
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dsb();
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}
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/*
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* mt_irq_mask: mask one IRQ
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* @irq: IRQ line of the IRQ to mask
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*/
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void mt_irq_mask(unsigned int irq) {
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unsigned int mask = 1 << (irq % 32);
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DRV_WriteReg32(GIC_DIST_BASE + GIC_DIST_ENABLE_CLEAR + irq / 32 * 4, mask);
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dsb();
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}
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/*
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* mt_irq_unmask: unmask one IRQ
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* @irq: IRQ line of the IRQ to unmask
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*/
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void mt_irq_unmask(unsigned int irq) {
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unsigned int mask = 1 << (irq % 32);
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DRV_WriteReg32(GIC_DIST_BASE + GIC_DIST_ENABLE_SET + irq / 32 * 4, mask);
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dsb();
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}
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/*
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* mt_irq_mask: mask one IRQ
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* @irq: IRQ line of the IRQ to mask
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*/
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void mt_irq_ack(unsigned int irq) {
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DRV_WriteReg32(GIC_CPU_BASE + GIC_CPU_EOI, irq);
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dsb();
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}
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/*
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* mt_irq_mask_all: mask all IRQ lines. (This is ONLY used for the sleep driver)
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* @mask: pointer to struct mtk_irq_mask for storing the original mask value.
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* Return 0 for success; return negative values for failure.
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*/
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int mt_irq_mask_all(struct mtk_irq_mask *mask) {
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if (mask) {
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mask->mask0 = DRV_Reg32(GIC_ICDISER0);
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mask->mask1 = DRV_Reg32(GIC_ICDISER1);
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mask->mask2 = DRV_Reg32(GIC_ICDISER2);
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mask->mask3 = DRV_Reg32(GIC_ICDISER3);
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mask->mask4 = DRV_Reg32(GIC_ICDISER4);
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mask->mask5 = DRV_Reg32(GIC_ICDISER5);
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mask->mask6 = DRV_Reg32(GIC_ICDISER6);
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mask->mask7 = DRV_Reg32(GIC_ICDISER7);
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DRV_WriteReg32(GIC_ICDICER0, 0xFFFFFFFF);
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DRV_WriteReg32(GIC_ICDICER1, 0xFFFFFFFF);
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DRV_WriteReg32(GIC_ICDICER2, 0xFFFFFFFF);
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DRV_WriteReg32(GIC_ICDICER3, 0xFFFFFFFF);
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DRV_WriteReg32(GIC_ICDICER4, 0xFFFFFFFF);
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DRV_WriteReg32(GIC_ICDICER5, 0xFFFFFFFF);
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DRV_WriteReg32(GIC_ICDICER6, 0xFFFFFFFF);
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DRV_WriteReg32(GIC_ICDICER7, 0xFFFFFFFF);
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dsb();
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mask->header = IRQ_MASK_HEADER;
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mask->footer = IRQ_MASK_FOOTER;
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return 0;
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} else {
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return -1;
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}
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}
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/*
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* mt_irq_mask_restore: restore all IRQ lines' masks. (This is ONLY used for the sleep driver)
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* @mask: pointer to struct mtk_irq_mask for storing the original mask value.
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* Return 0 for success; return negative values for failure.
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*/
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int mt_irq_mask_restore(struct mtk_irq_mask *mask) {
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if (!mask) {
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return -1;
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}
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if (mask->header != IRQ_MASK_HEADER) {
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return -1;
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}
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if (mask->footer != IRQ_MASK_FOOTER) {
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return -1;
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}
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DRV_WriteReg32(GIC_ICDISER0,mask->mask0);
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DRV_WriteReg32(GIC_ICDISER1,mask->mask1);
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DRV_WriteReg32(GIC_ICDISER2,mask->mask2);
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DRV_WriteReg32(GIC_ICDISER3,mask->mask3);
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DRV_WriteReg32(GIC_ICDISER4,mask->mask4);
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DRV_WriteReg32(GIC_ICDISER5,mask->mask5);
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DRV_WriteReg32(GIC_ICDISER6,mask->mask6);
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DRV_WriteReg32(GIC_ICDISER7,mask->mask7);
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dsb();
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return 0;
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}
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