9a4fae0714
Also remove a few extra data structures that were marked packed but not otherwise used anywhere.
213 lines
6.5 KiB
C
213 lines
6.5 KiB
C
/*
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* Copyright (c) 2009 Corey Tabaka
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* Copyright (c) 2021 Travis Geiseblrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#pragma once
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#include <assert.h>
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#include <sys/types.h>
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#include <lk/compiler.h>
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// This file contains defines and structures for the PCI bus independent
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// of any devices or drivers that may use them.
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__BEGIN_CDECLS
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/*
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* PCI configuration space offsets
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*/
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#define PCI_CONFIG_VENDOR_ID 0x00
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#define PCI_CONFIG_DEVICE_ID 0x02
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#define PCI_CONFIG_COMMAND 0x04
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#define PCI_CONFIG_STATUS 0x06
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#define PCI_CONFIG_REVISION_ID 0x08
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#define PCI_CONFIG_CLASS_CODE 0x09
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#define PCI_CONFIG_CLASS_CODE_INTR 0x09
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#define PCI_CONFIG_CLASS_CODE_SUB 0x0a
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#define PCI_CONFIG_CLASS_CODE_BASE 0x0b
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#define PCI_CONFIG_CACHE_LINE_SIZE 0x0c
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#define PCI_CONFIG_LATENCY_TIMER 0x0d
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#define PCI_CONFIG_HEADER_TYPE 0x0e
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#define PCI_CONFIG_BIST 0x0f
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/* Type 0 */
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#define PCI_CONFIG_BASE_ADDRESSES 0x10
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#define PCI_CONFIG_CARDBUS_CIS_PTR 0x28
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#define PCI_CONFIG_SUBSYS_VENDOR_ID 0x2c
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#define PCI_CONFIG_SUBSYS_ID 0x2e
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#define PCI_CONFIG_EXP_ROM_ADDRESS 0x30
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#define PCI_CONFIG_CAPABILITIES 0x34
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#define PCI_CONFIG_INTERRUPT_LINE 0x3c
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#define PCI_CONFIG_INTERRUPT_PIN 0x3d
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#define PCI_CONFIG_MIN_GRANT 0x3e
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#define PCI_CONFIG_MAX_LATENCY 0x3f
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/*
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* PCI header type register bits
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*/
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#define PCI_HEADER_TYPE_MASK 0x7f
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#define PCI_HEADER_TYPE_MULTI_FN 0x80
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/*
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* PCI header types
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*/
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#define PCI_HEADER_TYPE_STANDARD 0x00
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#define PCI_HEADER_TYPE_PCI_BRIDGE 0x01
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#define PCI_HEADER_TYPE_CARD_BUS 0x02
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/*
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* PCI command register bits
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*/
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#define PCI_COMMAND_IO_EN 0x0001
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#define PCI_COMMAND_MEM_EN 0x0002
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#define PCI_COMMAND_BUS_MASTER_EN 0x0004
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#define PCI_COMMAND_SPECIAL_EN 0x0008
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#define PCI_COMMAND_MEM_WR_INV_EN 0x0010
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#define PCI_COMMAND_PAL_SNOOP_EN 0x0020
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#define PCI_COMMAND_PERR_RESP_EN 0x0040
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#define PCI_COMMAND_AD_STEP_EN 0x0080
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#define PCI_COMMAND_SERR_EN 0x0100
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#define PCI_COMMAND_FAST_B2B_EN 0x0200
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/*
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* PCI status register bits
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*/
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#define PCI_STATUS_NEW_CAPS 0x0010
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#define PCI_STATUS_66_MHZ 0x0020
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#define PCI_STATUS_FAST_B2B 0x0080
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#define PCI_STATUS_MSTR_PERR 0x0100
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#define PCI_STATUS_DEVSEL_MASK 0x0600
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#define PCI_STATUS_TARG_ABORT_SIG 0x0800
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#define PCI_STATUS_TARG_ABORT_RCV 0x1000
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#define PCI_STATUS_MSTR_ABORT_RCV 0x2000
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#define PCI_STATUS_SERR_SIG 0x4000
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#define PCI_STATUS_PERR 0x8000
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/* structure version of the standard pci config space */
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typedef struct {
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uint16_t vendor_id;
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uint16_t device_id;
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uint16_t command;
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uint16_t status;
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uint8_t revision_id_0;
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uint8_t program_interface;
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uint8_t sub_class;
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uint8_t base_class;
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uint8_t cache_line_size;
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uint8_t latency_timer;
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uint8_t header_type;
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uint8_t bist;
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/* offset 0x10 */
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union {
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struct {
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uint32_t base_addresses[6];
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uint32_t cardbus_cis_ptr;
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uint16_t subsystem_vendor_id;
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uint16_t subsystem_id;
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uint32_t expansion_rom_address;
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uint8_t capabilities_ptr;
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uint8_t reserved_0[3];
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uint32_t reserved_1;
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uint8_t interrupt_line;
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uint8_t interrupt_pin;
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uint8_t min_grant;
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uint8_t max_latency;
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} type0; // configuration for normal devices
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struct {
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uint32_t base_addresses[2];
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uint8_t primary_bus;
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uint8_t secondary_bus;
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uint8_t subordinate_bus;
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uint8_t secondary_latency_timer;
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uint8_t io_base;
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uint8_t io_limit;
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uint16_t secondary_status;
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uint16_t memory_base;
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uint16_t memory_limit;
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uint16_t prefetchable_memory_base;
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uint16_t prefetchable_memory_limit;
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uint32_t prefetchable_base_upper;
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uint32_t prefetchable_limit_upper;
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uint16_t io_base_upper;
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uint16_t io_limit_upper;
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uint8_t capabilities_ptr;
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uint8_t reserved_0[3];
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uint32_t expansion_rom_address;
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uint8_t interrupt_line;
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uint8_t interrupt_pin;
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uint16_t bridge_control;
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} type1; // configuration for bridge devices
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};
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} pci_config_t;
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static_assert(sizeof(pci_config_t) == 0x40, "");
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/* Class/subclass codes (incomplete) */
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#define PCI_SUBCLASS_OTHER 0x80 // common 'other' in many of the subclasses
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#define PCI_CLASS_UNCLASSIFIED 0x0
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#define PCI_SUBCLASS_NON_VGA_UNCLASSIFIED 0x0
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#define PCI_SUBCLASS_VGA_UNCLASSIFIED 0x1
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#define PCI_CLASS_MASS_STORAGE 0x1
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#define PCI_SUBCLASS_SCSI 0x0
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#define PCI_SUBCLASS_IDE 0x1
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#define PCI_SUBCLASS_FLOPPY 0x2
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#define PCI_SUBCLASS_IPI 0x3
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#define PCI_SUBCLASS_RAID 0x4
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#define PCI_SUBCLASS_ATA 0x5
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#define PCI_SUBCLASS_SERIAL_ATA 0x6
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#define PCI_SUBCLASS_SAS 0x7
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#define PCI_SUBCLASS_NON_VOLATILE 0x8
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#define PCI_CLASS_NETWORK 0x2
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#define PCI_SUBCLASS_ETHERNET 0x0
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#define PCI_SUBCLASS_TOKEN_RING 0x1
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#define PCI_SUBCLASS_FDDI 0x2
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#define PCI_SUBCLASS_ATM 0x3
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#define PCI_SUBCLASS_ISDN 0x4
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#define PCI_SUBCLASS_WORLDFIP 0x5
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#define PCI_SUBCLASS_PICMG 0x6
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#define PCI_SUBCLASS_INFINIBAND 0x7
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#define PCI_CLASS_DISPLAY 0x3
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#define PCI_SUBCLASS_VGA 0x0
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#define PCI_SUBCLASS_XGA 0x1
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#define PCI_SUBCLASS_3D 0x2
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#define PCI_CLASS_MULTIMEDIA 0x4
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#define PCI_CLASS_MEMORY 0x5
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#define PCI_CLASS_BRIDGE 0x6
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#define PCI_SUBCLASS_HOST_BRIDGE 0x0
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#define PCI_SUBCLASS_ISA_BRIDGE 0x1
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#define PCI_SUBCLASS_EISA_BRIDGE 0x2
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#define PCI_SUBCLASS_MCA_BRIDGE 0x3
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#define PCI_SUBCLASS_PCI_PCI_BRIDGE 0x4
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#define PCI_SUBCLASS_PCMCIA_BRIDGE 0x5
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#define PCI_SUBCLASS_NUBUS_BRIDGE 0x6
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#define PCI_SUBCLASS_CARDBUS_BRIDGE 0x7
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#define PCI_SUBCLASS_RACEWAY_BRIDGE 0x8
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#define PCI_SUBCLASS_PCI_PCI_BRIDGE2 0x9
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#define PCI_SUBCLASS_INFINIBAND_TO_PCI_BRIDGE 0xa
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#define PCI_CLASS_SIMPLE_COMMS 0x7
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#define PCI_CLASS_BASE_PERIPH 0x8
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#define PCI_CLASS_INPUT 0x9
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#define PCI_CLASS_DOCKING_STATION 0xa
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#define PCI_CLASS_PROCESSOR 0xb
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#define PCI_CLASS_SERIAL_BUS 0xc
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#define PCI_CLASS_WIRELESS 0xd
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#define PCI_CLASS_INTELLIGENT_CONTROLLER 0xe
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#define PCI_CLASS_SATELLITE 0xf
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#define PCI_CLASS_ENCRYPTION 0x10
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#define PCI_CLASS_SIGNAL_PROCESSING 0x11
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#define PCI_CLASS_PROCESSING_ACCEL 0x12
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#define PCI_CLASS_COPROCESSOR 0x40
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#define PCI_CLASS_UNASSIGNED 0xff
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__END_CDECLS
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