3ea007a237
It's getting too hard to maintain a single layout that works with both, so go ahead and split it. Also redo the layout so it should be usable with user space and syscall and sysenter instructions from either mode.
122 lines
4.0 KiB
ArmAsm
122 lines
4.0 KiB
ArmAsm
/*
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* Copyright (c) 2009 Corey Tabaka
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* Copyright (c) 2015 Intel Corporation
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* Copyright (c) 2016 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include <lk/asm.h>
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#include <arch/x86/descriptor.h>
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#define PHYS_LOAD_ADDRESS (MEMBASE + KERNEL_LOAD_OFFSET)
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#define PHYS_ADDR_DELTA (KERNEL_BASE + KERNEL_LOAD_OFFSET - PHYS_LOAD_ADDRESS)
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#define PHYS(x) ((x) - PHYS_ADDR_DELTA)
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.section .rodata
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.balign 8
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DATA(_gdtr_phys)
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.short _gdt_end - _gdt - 1
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.int PHYS(_gdt)
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END_DATA(_gdtr_phys)
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.balign 8
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DATA(_gdtr)
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.short _gdt_end - _gdt - 1
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.quad _gdt
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END_DATA(_gdtr)
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// 64bit GDT, laid out in a specific way due to requirements by the SYSENTER/SYSEXIT and
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// SYSCALL/SYSRET instructions:
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//
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// CODE32 (for bootstrap purposes)
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// CODE64 <- IA32_SYSENTER_CS, IA32_STAR.SYSCALL_CS
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// DATA64
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// UCODE32 <- IA32_STAR.SYSRET_CS
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// UDATA32
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// UCODE64
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// UDATA64 (optional if no 64bit sysenter support)
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.data
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.balign 8
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DATA(_gdt)
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.int 0
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.int 0
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/* ring 0 code 32bit (for bootstrapping into 64bit) */
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.short 0xffff /* limit 15:00 */
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.short 0x0000 /* base 15:00 */
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.byte 0x00 /* base 23:16 */
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.byte 0b10011010 /* P(1) DPL(00) S(1) 1 C(0) R(1) A(0) */
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.byte 0b11001111 /* G(1) D(1) 0 0 limit 19:16 */
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.byte 0x0 /* base 31:24 */
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/* ring 0 code 64bit */
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.short 0xffff /* limit 15:00 */
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.short 0x0000 /* base 15:00 */
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.byte 0x00 /* base 23:16 */
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.byte 0b10011010 /* P(1) DPL(00) S(1) 1 C(0) R(1) A(0) */
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.byte 0b10101111 /* G(1) D(0) L(1) AVL(0) limit 19:16 */
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.byte 0x0 /* base 31:24 */
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/* ring 0 data 64bit */
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.short 0xffff /* limit 15:00 */
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.short 0x0000 /* base 15:00 */
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.byte 0x00 /* base 23:16 */
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.byte 0b10010010 /* P(1) DPL(00) S(1) 0 E(0) W(1) A(0) */
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.byte 0b11001111 /* G(1) B(1) 0 0 limit 19:16 */
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.byte 0x0 /* base 31:24 */
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/* ring 3 code 32bit */
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.short 0xffff /* limit 15:00 */
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.short 0x0000 /* base 15:00 */
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.byte 0x00 /* base 23:16 */
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.byte 0b11111010 /* P(1) DPL(11) S(1) 1 C(0) R(1) A(0) */
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.byte 0b11001111 /* G(1) D(1) 0 0 limit 19:16 */
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.byte 0x0 /* base 31:24 */
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/* ring 3 data 32bit */
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.short 0xffff /* limit 15:00 */
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.short 0x0000 /* base 15:00 */
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.byte 0x00 /* base 23:16 */
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.byte 0b11110010 /* P(1) DPL(11) S(1) 0 E(0) W(1) A(0) */
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.byte 0b11001111 /* G(1) B(1) 0 0 limit 19:16 */
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.byte 0x0 /* base 31:24 */
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/* ring 3 code 64bit */
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.short 0xffff /* limit 15:00 */
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.short 0x0000 /* base 15:00 */
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.byte 0x00 /* base 23:16 */
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.byte 0b11111010 /* P(1) DPL(11) S(1) 1 C(0) R(1) A(0) */
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.byte 0b10101111 /* G(1) D(1) L(0) AVL(0) limit 19:16 */
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.byte 0x0 /* base 31:24 */
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/* ring 3 data 64bit */
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.short 0xffff /* limit 15:00 */
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.short 0x0000 /* base 15:00 */
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.byte 0x00 /* base 23:16 */
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.byte 0b11110010 /* P(1) DPL(11) S(1) 0 E(0) W(1) A(0) */
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.byte 0b11001111 /* G(1) B(1) 0 0 limit 19:16 */
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.byte 0x0 /* base 31:24 */
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/* per-cpu TSS descriptor */
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.set i, 1
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.rept SMP_MAX_CPUS
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.short 0 /* limit 15:00 */
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.short 0 /* base 15:00 */
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.byte 0 /* base 23:16 */
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.byte 0x89 /* P(1) DPL(00) S(0) TYPE(9) */
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.byte 0x80 /* G(1) D/B(0) L(0) AVL(0) limit 19:16 */
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.byte 0 /* base 31:24 */
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/* 64-bit TSSs are 16 bytes long */
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.int 0 /* base 63:32 */
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.int 0 /* type(0) + reserved */
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.set i, i+1
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.endr
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END_DATA(_gdt)
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DATA(_gdt_end)
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