6f32a0f377
I hadn't noticed this before, but you can directly reference a global variable in a load/store in assembly, which combines a lla + ld/sd into a 2 instruction pair instead of 3 due to the 12 bit offset provided in the load/store.
258 lines
6.6 KiB
ArmAsm
258 lines
6.6 KiB
ArmAsm
/*
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* Copyright (c) 2015 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include <lk/asm.h>
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#include <arch/defines.h>
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#include <arch/riscv/asm.h>
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#include <arch/riscv/mmu.h>
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#include "config.h"
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.section ".text.boot"
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FUNCTION(_start)
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.option push
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.option norelax
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// set the global pointer
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lla gp, __global_pointer$
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.option pop
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#if RISCV_M_MODE
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// copy the hart id into a0 which we'll use later
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// supervisor mode should already have hart id in a0
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csrr a0, mhartid
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#endif
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// cpu lottery: whoever sets this first gets to be cpu 0
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lla t0, _boot_lottery
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li t1, 1
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amoadd.w a2, t1, (t0)
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// a2 now holds the logical cpu number. a2 is used because it is
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// the first unused argument register on SBI based systems,
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// which seem to use a0 and a1.
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// if this cpu is out of range, trap it
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li t0, SMP_MAX_CPUS
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ble t0, a2, hart_trap
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// set the default stack per cpu
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lla sp, default_stack_top
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// default stack locations for each cpu:
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// LOW ------------ HIGH
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// [cpu2][cpu1][cpu0]
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li t1, ARCH_DEFAULT_STACK_SIZE
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mul t1, t1, a2
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sub sp, sp, t1
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// if we aren't cpu 0, go hang out in secondary cpu purgatory for now
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bne a2, zero, secondary_trap
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#if ARCH_RISCV_TWOSEGMENT
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// copy preinitialized data from flash to memory
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lla t0, __data_start_rom
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lla t1, __data_start
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lla t2, __data_end
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beq t0, t1, 1f
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0:
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LDR t3, (t0)
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STR t3, (t1)
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add t0, t0, RISCV_XLEN_BYTES
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add t1, t1, RISCV_XLEN_BYTES
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bne t1, t2, 0b
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#endif
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// zero bss
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1:
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lla t0, __bss_start
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lla t1, __bss_end
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beq t0, t1, 1f
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0:
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STR zero, (t0)
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add t0, t0, RISCV_XLEN_BYTES
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bne t0, t1, 0b
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1:
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#if WITH_SMP
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// Save a copy of _start in physical space. This is later used
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// as the entry point for secondary cpus.
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lla t0, _start
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STR t0, (_start_physical), t1
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#endif
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#if RISCV_MMU
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call _mmu_init
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#endif
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#if WITH_SMP
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// Release any other harts into riscv_secondary_entry
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fence w, w
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li t0, 1
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sb t0, (_boot_status), t1
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fence
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#endif
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// call into early C code to set up the percpu structure
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mv s0, a0
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mv s1, a1
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mv s2, a2
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mv s3, a3
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call riscv_configure_percpu_early
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mv a0, s0
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mv a1, s1
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mv a2, s2
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mv a3, s3
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// call main
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call lk_main
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// should never return here
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j .
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END_FUNCTION(_start)
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LOCAL_FUNCTION(secondary_trap)
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#if WITH_SMP
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// wait for _boot_status to be nonzero, then go into riscv_secondary_entry
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lb t0, (_boot_status)
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beqz t0, secondary_trap
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// we've been released by the main cpu and/or we've been booted after the
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// system has been running a while.
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#if RISCV_MMU
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// enable the mmu on this core
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call .Lenable_mmu
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#endif
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// a0 == hart id
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// a2 == assigned cpu id (may not be the same)
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// set the per cpu structure before getting into the secondary boot path
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call riscv_configure_percpu_early
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// bootstrap the secondary cpus
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call riscv_secondary_entry
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#endif
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// fallthrough if either no SMP or riscv_secondary_entry returns
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END_FUNCTION(secondary_trap)
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LOCAL_FUNCTION(hart_trap)
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// cpus with too high of a hart id go here and spin forever
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wfi
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j hart_trap
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END_FUNCTION(hart_trap)
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#if RISCV_MMU
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// initialize the kernel page tables
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// for all MMU versions, identity map some amount of memory near 0 and
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// the same amount at the bottom of the kernel's address space
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LOCAL_FUNCTION(_mmu_init)
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lla t0, trampoline_pgtable
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// store the physical address of the pgtable for future use
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sd t0, (trampoline_pgtable_phys), t1
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// do the same for the main kernel pgtable
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lla t2, kernel_pgtable
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sd t2, (kernel_pgtable_phys), t1
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// and the 2nd level tables
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lla t2, kernel_l2_pgtable
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sd t2, (kernel_l2_pgtable_phys), t1
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// compute kernel pgtable pointer (index 256)
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addi t1, t0, (8 * 128)
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addi t1, t1, (8 * 128)
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// page table entry: address 0, A, D, G, XWR, V
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li t2, (0 | (1<<7) | (1<<6) | (1<<5) | (1<<3) | (1<<2) | (1<<1) | (1<<0))
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// num interations and increment count
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#if RISCV_MMU == 48 || RISCV_MMU == 39
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// RV48: map the first 512GB of the physical address space at the
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// bottom of the kernel address space using a single terapage
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// RV39: map the first 64GB of the physical address space at the
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// bottom of the kernel address space using 64 1GB gigapages
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li t3, RISCV_MMU_PHYSMAP_PAGE_COUNT
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li t4, (RISCV_MMU_PHYSMAP_PAGE_SIZE >> 2)
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#else
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#error implement sv32
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#endif
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// loop, writing t3 entries out and incrementing by t4 address.
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// write both to t0 (index 0 of the kernel page table) and
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// t1 (starting index of kernel space)
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0:
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sd t2, (t1)
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sd t2, (t0)
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add t2, t2, t4
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addi t0, t0, 8
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addi t1, t1, 8
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addi t3, t3, -1
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bnez t3, 0b
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// ensure it's written out
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fence w,w
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.Lenable_mmu:
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// set the satp register and enable the mmu
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// ASID 0, trampoline_pgtable address
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lla t0, trampoline_pgtable
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srli t1, t0, 12
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#if RISCV_MMU == 48
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li t2, (RISCV_SATP_MODE_SV48 << RISCV_SATP_MODE_SHIFT)
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#elif RISCV_MMU == 39
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li t2, (RISCV_SATP_MODE_SV39 << RISCV_SATP_MODE_SHIFT)
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#else
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#error implement
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#endif
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or t1, t1, t2
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csrw satp, t1
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// global tlb fence
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sfence.vma zero, zero
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// mmu is initialized and we're running out of an identity physical map
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// save the physical address of .Lhigh
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lla t1, .Lhigh
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// bounce to the high address
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ld t0, (.Lhigh_addr)
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jr t0
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// the full virtual address of the .Lhigh label
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.Lhigh_addr:
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.quad .Lhigh
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.Lhigh:
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// we're now running at the high virtual address
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// compute the delta between the old physical and newer high addresses
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sub t0, t0, t1
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// fix up the gp, stack pointer, and return address
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add gp, gp, t0
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add sp, sp, t0
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add ra, ra, t0
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ret
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END_FUNCTION(_mmu_init)
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#endif // RISCV_MMU
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.bss
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.align 4
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LOCAL_DATA(default_stack)
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.skip ARCH_DEFAULT_STACK_SIZE * SMP_MAX_CPUS
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LOCAL_DATA(default_stack_top)
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// put boot status in .data so it doesn't get paved over during BSS initialization
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.data
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LOCAL_DATA(_boot_status)
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.byte 0
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.align 2
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LOCAL_DATA(_boot_lottery)
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.word 0
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