b0d8aeed18
Currently only implemented for double precision floating point. Caveat: currently unable to only compile some code with or without float. The linker is extremely picky about mixing float and no-float objects, so stick with all on or off for now. It's not as much of a problem currently because the toolchain is not using any riscv vector instructions to assist normal code, so it's generally only emitting fpu instructions for floating point code.
160 lines
3.7 KiB
ArmAsm
160 lines
3.7 KiB
ArmAsm
/*
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* Copyright (c) 2022 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include <lk/asm.h>
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#include <arch/riscv.h>
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#include <arch/riscv/asm.h>
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#if RISCV_FPU
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// enable full use of all of the fpu instructions
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#if __riscv_xlen == 32
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.attribute arch, "rv32imafdc"
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#elif __riscv_xlen == 64
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.attribute arch, "rv64imafdc"
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#else
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#error unknown xlen
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#endif
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// conditionally use fcvt or fmv based on 32 or 64bit ISA
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.macro ZERO_FPU_REG reg, width
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#if __riscv_xlen == 32
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fcvt.\width\().w \reg, zero
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#elif __riscv_xlen == 64
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fmv.\width\().x \reg, zero
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#endif
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.endm
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// called just before entering user space for the first time.
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// must not use the stack and is okay to be called with interrupts disabled.
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FUNCTION(riscv_fpu_zero)
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// zero out the fpu state
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// TODO: handle single precision implementations
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csrw fcsr, zero
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ZERO_FPU_REG f0, d
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ZERO_FPU_REG f1, d
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ZERO_FPU_REG f2, d
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ZERO_FPU_REG f3, d
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ZERO_FPU_REG f4, d
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ZERO_FPU_REG f5, d
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ZERO_FPU_REG f6, d
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ZERO_FPU_REG f7, d
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ZERO_FPU_REG f8, d
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ZERO_FPU_REG f9, d
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ZERO_FPU_REG f10, d
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ZERO_FPU_REG f11, d
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ZERO_FPU_REG f12, d
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ZERO_FPU_REG f13, d
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ZERO_FPU_REG f14, d
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ZERO_FPU_REG f15, d
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ZERO_FPU_REG f16, d
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ZERO_FPU_REG f17, d
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ZERO_FPU_REG f18, d
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ZERO_FPU_REG f19, d
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ZERO_FPU_REG f20, d
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ZERO_FPU_REG f21, d
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ZERO_FPU_REG f22, d
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ZERO_FPU_REG f23, d
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ZERO_FPU_REG f24, d
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ZERO_FPU_REG f25, d
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ZERO_FPU_REG f26, d
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ZERO_FPU_REG f27, d
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ZERO_FPU_REG f28, d
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ZERO_FPU_REG f29, d
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ZERO_FPU_REG f30, d
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ZERO_FPU_REG f31, d
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// put the hardware in the initial state
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// FS[1:0] == 1 set in two steps: one to set bit 0, second one to clear bit 1
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// this ensures it doesn't go through the disabled state (00)
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li a0, (1 << 13)
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csrs RISCV_CSR_XSTATUS, a0
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li a0, (1 << 14)
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csrc RISCV_CSR_XSTATUS, a0
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ret
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END_FUNCTION(riscv_fpu_zero)
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// void riscv_fpu_save(struct riscv_fpu_state *state);
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FUNCTION(riscv_fpu_save)
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fsd f0, 0*8(a0)
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fsd f1, 1*8(a0)
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fsd f2, 2*8(a0)
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fsd f3, 3*8(a0)
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fsd f4, 4*8(a0)
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fsd f5, 5*8(a0)
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fsd f6, 6*8(a0)
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fsd f7, 7*8(a0)
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fsd f8, 8*8(a0)
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fsd f9, 9*8(a0)
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fsd f10, 10*8(a0)
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fsd f11, 11*8(a0)
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fsd f12, 12*8(a0)
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fsd f13, 13*8(a0)
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fsd f14, 14*8(a0)
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fsd f15, 15*8(a0)
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fsd f16, 16*8(a0)
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fsd f17, 17*8(a0)
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fsd f18, 18*8(a0)
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fsd f19, 19*8(a0)
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fsd f20, 20*8(a0)
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fsd f21, 21*8(a0)
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fsd f22, 22*8(a0)
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fsd f23, 23*8(a0)
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fsd f24, 24*8(a0)
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fsd f25, 25*8(a0)
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fsd f26, 26*8(a0)
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fsd f27, 27*8(a0)
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fsd f28, 28*8(a0)
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fsd f29, 29*8(a0)
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fsd f30, 30*8(a0)
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fsd f31, 31*8(a0)
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csrr a1, fcsr
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sw a1, 32*8(a0)
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ret
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END_FUNCTION(riscv_fpu_save)
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// void riscv_fpu_restore(struct riscv_fpu_state *state);
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FUNCTION(riscv_fpu_restore)
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fld f0, 0*8(a0)
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fld f1, 1*8(a0)
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fld f2, 2*8(a0)
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fld f3, 3*8(a0)
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fld f4, 4*8(a0)
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fld f5, 5*8(a0)
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fld f6, 6*8(a0)
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fld f7, 7*8(a0)
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fld f8, 8*8(a0)
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fld f9, 9*8(a0)
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fld f10, 10*8(a0)
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fld f11, 11*8(a0)
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fld f12, 12*8(a0)
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fld f13, 13*8(a0)
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fld f14, 14*8(a0)
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fld f15, 15*8(a0)
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fld f16, 16*8(a0)
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fld f17, 17*8(a0)
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fld f18, 18*8(a0)
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fld f19, 19*8(a0)
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fld f20, 20*8(a0)
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fld f21, 21*8(a0)
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fld f22, 22*8(a0)
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fld f23, 23*8(a0)
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fld f24, 24*8(a0)
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fld f25, 25*8(a0)
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fld f26, 26*8(a0)
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fld f27, 27*8(a0)
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fld f28, 28*8(a0)
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fld f29, 29*8(a0)
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fld f30, 30*8(a0)
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fld f31, 31*8(a0)
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lw a1, 32*8(a0)
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csrw fcsr, a1
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ret
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END_FUNCTION(riscv_fpu_restore)
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#endif // RISCV_FPU
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