d3cd5be13e
Instead of ICACHE/DCACHE/UCACHE, add the ARCH_CACHE_FLAG_ prefix to be a little cleaner and not collide with anything else. No functional change.
107 lines
2.8 KiB
C
107 lines
2.8 KiB
C
/*
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* Copyright (c) 2015 Stefan Kristiansson
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include <arch/ops.h>
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#include <arch/or1k.h>
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static inline uint32_t dc_block_size(void) {
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uint32_t dccfgr = mfspr(OR1K_SPR_SYS_DCCFGR_ADDR);
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return dccfgr & OR1K_SPR_SYS_DCCFGR_CBS_MASK ? 32 : 16;
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}
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static inline uint32_t dc_sets(void) {
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uint32_t dccfgr = mfspr(OR1K_SPR_SYS_DCCFGR_ADDR);
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return 1 << OR1K_SPR_SYS_DCCFGR_NCS_GET(dccfgr);
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}
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static inline uint32_t ic_block_size(void) {
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uint32_t iccfgr = mfspr(OR1K_SPR_SYS_ICCFGR_ADDR);
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return iccfgr & OR1K_SPR_SYS_ICCFGR_CBS_MASK ? 32 : 16;
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}
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static inline uint32_t ic_sets(void) {
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uint32_t iccfgr = mfspr(OR1K_SPR_SYS_ICCFGR_ADDR);
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return 1 << OR1K_SPR_SYS_ICCFGR_NCS_GET(iccfgr);
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}
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void arch_invalidate_cache_all(void) {
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uint32_t i;
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uint32_t cache_size;
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uint32_t block_size;
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block_size = ic_block_size();
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cache_size = block_size * ic_sets();
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for (i = 0; i < cache_size; i += block_size)
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mtspr(OR1K_SPR_ICACHE_ICBIR_ADDR, i);
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block_size = dc_block_size();
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cache_size = block_size * dc_sets();
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for (i = 0; i < cache_size; i += block_size)
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mtspr(OR1K_SPR_DCACHE_DCBIR_ADDR, i);
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}
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void arch_disable_cache(uint flags) {
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uint32_t sr = mfspr(OR1K_SPR_SYS_SR_ADDR);
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if (flags & ARCH_CACHE_FLAG_ICACHE)
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sr &= ~OR1K_SPR_SYS_SR_ICE_MASK;
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if (flags & ARCH_CACHE_FLAG_DCACHE)
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sr &= ~OR1K_SPR_SYS_SR_DCE_MASK;
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mtspr(OR1K_SPR_SYS_SR_ADDR, sr);
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}
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void arch_enable_cache(uint flags) {
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uint32_t sr = mfspr(OR1K_SPR_SYS_SR_ADDR);
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if (flags & ARCH_CACHE_FLAG_ICACHE)
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sr |= OR1K_SPR_SYS_SR_ICE_MASK;
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if (flags & ARCH_CACHE_FLAG_DCACHE)
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sr |= OR1K_SPR_SYS_SR_DCE_MASK;
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mtspr(OR1K_SPR_SYS_SR_ADDR, sr);
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}
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/* flush dcache */
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void arch_clean_cache_range(addr_t start, size_t len) {
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addr_t addr;
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uint32_t block_size = dc_block_size();
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for (addr = start; addr < start + len; addr += block_size)
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mtspr(OR1K_SPR_DCACHE_DCBFR_ADDR, addr);
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}
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/* invalidate dcache */
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void arch_invalidate_cache_range(addr_t start, size_t len) {
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addr_t addr;
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uint32_t block_size = dc_block_size();
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for (addr = start; addr < start + len; addr += block_size)
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mtspr(OR1K_SPR_DCACHE_DCBIR_ADDR, addr);
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}
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/* flush + invalidate dcache */
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void arch_clean_invalidate_cache_range(addr_t start, size_t len) {
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/* invalidate is implied by flush on or1k */
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arch_clean_cache_range(start, len);
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}
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/* flush dcache + invalidate icache */
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void arch_sync_cache_range(addr_t start, size_t len) {
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addr_t addr;
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uint32_t block_size = ic_block_size();
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arch_clean_cache_range(start, len);
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for (addr = start; addr < start + len; addr += block_size)
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mtspr(OR1K_SPR_ICACHE_ICBIR_ADDR, addr);
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}
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