e47183725d
- Make the secondary entry point be logically separate function, though declared in the same file. - Add a trick where the kernel base + 4 is the secondary entry point. Not really useful except makes it easy to compute the offset elsewhere. - Changed the entry point to arm64_reset and move _start to the linker script, which is what most other arches do. - While was in the linker script, make sure the text segment is aligned on MAXPAGESIZE, though doesn't make any real difference currently. - Generally clean up the assembly in start.S with newer macros from Fuchsia, and avoid using ldr X, =value as much as possible. - Fix and make sure arm64 can build and run with WITH_SMP set to false. Add a new no-smp project to test this. Note this will likely break systems where all of the cpus enter the kernel simultaneously, which we can fix if that becomes an issue. Secondary code now completely assumes the cpu number is passed in x0. This can be emulated with platform specific trampoline code if it needs to that then just directs into the the secondary entry point, instead of trying to make the arch code have to deal with all cases.
222 lines
4.4 KiB
ArmAsm
222 lines
4.4 KiB
ArmAsm
/*
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* Copyright (c) 2014 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include <lk/asm.h>
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#include <arch/asm_macros.h>
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.section .text.boot.vectab
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.p2align 11
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#define lr x30
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#define regsave_long_offset 0xf0
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#define regsave_short_offset 0x90
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// NOTE: stay in sync with arm64_iframe_long et al. in include/arch/arm64.h
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.macro regsave_long
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sub sp, sp, #32
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push x28, x29
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push x26, x27
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push x24, x25
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push x22, x23
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push x20, x21
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push x18, x19
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push x16, x17
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push x14, x15
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push x12, x13
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push x10, x11
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push x8, x9
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push x6, x7
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push x4, x5
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push x2, x3
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push x0, x1
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mrs x0, sp_el0
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mrs x1, elr_el1
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mrs x2, spsr_el1
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stp lr, x0, [sp, #regsave_long_offset]
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stp x1, x2, [sp, #regsave_long_offset + 16]
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.endm
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.macro regsave_short
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sub sp, sp, #32
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push x16, x17
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push x14, x15
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push x12, x13
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push x10, x11
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push x8, x9
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push x6, x7
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push x4, x5
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push x2, x3
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push x0, x1
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mrs x0, sp_el0
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mrs x1, elr_el1
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mrs x2, spsr_el1
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stp lr, x0, [sp, #regsave_short_offset]
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stp x1, x2, [sp, #regsave_short_offset + 16]
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.endm
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.macro regrestore_long
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ldp lr, x0, [sp, #regsave_long_offset]
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ldp x1, x2, [sp, #regsave_long_offset + 16]
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msr sp_el0, x0
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msr elr_el1, x1
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msr spsr_el1, x2
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pop x0, x1
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pop x2, x3
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pop x4, x5
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pop x6, x7
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pop x8, x9
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pop x10, x11
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pop x12, x13
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pop x14, x15
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pop x16, x17
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pop xzr, x19 // Do not restore x18, it is our per cpu pointer
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pop x20, x21
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pop x22, x23
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pop x24, x25
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pop x26, x27
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pop x28, x29
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add sp, sp, #32
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.endm
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.macro regrestore_short
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ldp lr, x0, [sp, #regsave_short_offset]
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ldp x1, x2, [sp, #regsave_short_offset + 16]
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msr sp_el0, x0
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msr elr_el1, x1
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msr spsr_el1, x2
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pop x0, x1
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pop x2, x3
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pop x4, x5
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pop x6, x7
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pop x8, x9
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pop x10, x11
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pop x12, x13
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pop x14, x15
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pop x16, x17
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add sp, sp, #32
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.endm
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.macro invalid_exception, which
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regsave_long
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mov x1, #\which
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mov x0, sp
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bl arm64_invalid_exception
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b .
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.endm
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.macro irq_exception
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regsave_short
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msr daifclr, #1 /* reenable fiqs once elr and spsr have been saved */
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mov x0, sp
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bl platform_irq
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cbz x0, .Lirq_exception_no_preempt\@
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bl thread_preempt
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.Lirq_exception_no_preempt\@:
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msr daifset, #1 /* disable fiqs to protect elr and spsr restore */
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b arm64_exc_shared_restore_short
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.endm
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FUNCTION(arm64_exception_table)
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/* exceptions from current EL, using SP0 */
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LOCAL_FUNCTION(arm64_sync_exc_current_el_SP0)
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invalid_exception 0
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.org 0x080
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LOCAL_FUNCTION(arm64_irq_current_el_SP0)
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invalid_exception 1
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.org 0x100
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LOCAL_FUNCTION(arm64_fiq_current_el_SP0)
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invalid_exception 2
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.org 0x180
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LOCAL_FUNCTION(arm64_err_exc_current_el_SP0)
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invalid_exception 3
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/* exceptions from current EL, using SPx */
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.org 0x200
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LOCAL_FUNCTION(arm64_sync_exc_current_el_SPx)
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regsave_long
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mov x0, sp
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bl arm64_sync_exception
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b arm64_exc_shared_restore_long
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.org 0x280
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LOCAL_FUNCTION(arm64_irq_current_el_SPx)
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irq_exception
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.org 0x300
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LOCAL_FUNCTION(arm64_fiq_current_el_SPx)
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regsave_short
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mov x0, sp
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bl platform_fiq
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b arm64_exc_shared_restore_short
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.org 0x380
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LOCAL_FUNCTION(arm64_err_exc_current_el_SPx)
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invalid_exception 0x13
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/* exceptions from lower EL, running arm64 */
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.org 0x400
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LOCAL_FUNCTION(arm64_sync_exc_lower_el_64)
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regsave_long
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mov x0, sp
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bl arm64_sync_exception
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b arm64_exc_shared_restore_long
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.org 0x480
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LOCAL_FUNCTION(arm64_irq_lower_el_64)
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irq_exception
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.org 0x500
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LOCAL_FUNCTION(arm64_fiq_lower_el_64)
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regsave_short
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mov x0, sp
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bl platform_fiq
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b arm64_exc_shared_restore_short
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.org 0x580
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LOCAL_FUNCTION(arm64_err_exc_lower_el_64)
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invalid_exception 0x23
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/* exceptions from lower EL, running arm32 */
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.org 0x600
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LOCAL_FUNCTION(arm64_sync_exc_lower_el_32)
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regsave_long
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mov x0, sp
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bl arm64_sync_exception
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b arm64_exc_shared_restore_long
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.org 0x680
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LOCAL_FUNCTION(arm64_irq_lower_el_32)
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irq_exception
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.org 0x700
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LOCAL_FUNCTION(arm64_fiq_lower_el_32)
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regsave_short
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mov x0, sp
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bl platform_fiq
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b arm64_exc_shared_restore_short
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.org 0x780
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LOCAL_FUNCTION(arm64_err_exc_lower_el_32)
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invalid_exception 0x33
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END_FUNCTION(arm64_exception_table)
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LOCAL_FUNCTION(arm64_exc_shared_restore_long)
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regrestore_long
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eret
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END_FUNCTION(arm64_exc_shared_restore_long)
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LOCAL_FUNCTION(arm64_exc_shared_restore_short)
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regrestore_short
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eret
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END_FUNCTION(arm64_exc_shared_restore_short)
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