6e3edb87de
- protocol now correctly reports SWO and SWCLK clock rates on set - remove some debug printfs that were causing fw hangs (investigate later) - allow setting a 1MHz SWCLK rate - CMD_ATTACH now supports an argument to select one of several special reset or escape sequences: ATTACH_SWD_RESET: 60 HI, 4 LO, basic line reset ATTACH_JTAG_SWD: escape sequence for JTAG -> SWD mode switch ATTACH_DORMANT_TO_SWD: escape squence to exit dormant mode ATTACH_SWD_TO_DORMANT: and go back again - add special support for writing to DP TARGETSEL register (response phase must be ignored), needed for SWD multidrop support - bump protocol version to 1.3 - bump firmware version to 1.0 (it's long overdue)
59 lines
1.6 KiB
C
59 lines
1.6 KiB
C
/* swd.h
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*
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* Copyright 2011 Brian Swetland <swetland@frotz.net>
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef _SWDP_H_
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#define _SWDP_H_
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void swd_init(void);
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void swd_reset(unsigned kind);
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int swd_write(unsigned reg, unsigned val);
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int swd_read(unsigned reg, unsigned *val);
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unsigned swd_set_clock(unsigned khz);
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unsigned swo_set_clock(unsigned khz);
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void swd_hw_reset(int assert);
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void jtag_init(void);
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int jtag_io(unsigned count, unsigned tms, unsigned tdi, unsigned *tdo);
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// swdp_read/write() register codes
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// Park Stop Parity Addr3 Addr2 RnW APnDP Start
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#define RD_IDCODE 0b10100101
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#define RD_DPCTRL 0b10001101
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#define RD_RESEND 0b10010101
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#define RD_BUFFER 0b10111101
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#define WR_ABORT 0b10000001
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#define WR_DPCTRL 0b10101001
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#define WR_SELECT 0b10110001
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#define WR_BUFFER 0b10011001
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#define RD_AP0 0b10000111
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#define RD_AP1 0b10101111
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#define RD_AP2 0b10110111
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#define RD_AP3 0b10011111
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#define WR_AP0 0b10100011
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#define WR_AP1 0b10001011
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#define WR_AP2 0b10010011
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#define WR_AP3 0b10111011
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#endif
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