[acc] Change doubles to floats to make it lazily fit in a BT characteristic

- Revert to HAL spi since there's still a timing bug in the new WIP driver
- Add nrf_sensors app to poll the ACC and send data every 100 ms

app/nrf_sensors/nrf_sensors.c

@@ -0,0 +1,58 @@
+#include <app.h>
+#include <arch.h>
+#include <assert.h>
+#include <debug.h>
+#include <err.h>
+#include <kernel/event.h>
+#include <lk/init.h>
+#include <stdlib.h>
+#include <trace.h>
+#include <target/gpioconfig.h>
+#include <stm32f7xx.h>
+#include <stm32f7xx_hal_spi.h>
+#include <dev/accelerometer.h>
+
+
+/* This code reads from the accelerometer then sends the data over to the nRF chip
+ * every 100 milliseconds. */
+static void nrf_sensors_init(const struct app_descriptor *app)
+{
+}
+
+static void nrf_sensors_entry(const struct app_descriptor *app, void *args)
+{
+    position_vector_t pos_vector;
+
+    SPI_HandleTypeDef spi_handle;
+    spi_handle.Instance               = SPI5;
+    spi_handle.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_128;
+    spi_handle.Init.Direction         = SPI_DIRECTION_2LINES;
+    spi_handle.Init.CLKPhase          = SPI_PHASE_1EDGE;
+    spi_handle.Init.CLKPolarity       = SPI_POLARITY_LOW;
+    spi_handle.Init.DataSize          = SPI_DATASIZE_8BIT;
+    spi_handle.Init.FirstBit          = SPI_FIRSTBIT_MSB;
+    spi_handle.Init.TIMode            = SPI_TIMODE_DISABLE;
+    spi_handle.Init.CRCCalculation    = SPI_CRCCALCULATION_DISABLE;
+    spi_handle.Init.CRCPolynomial     = 7;
+    spi_handle.Init.NSS               = SPI_NSS_SOFT;
+    spi_handle.Init.Mode              = SPI_MODE_MASTER;
+
+    gpio_config(GPIO_NRF_CS, GPIO_OUTPUT);
+    gpio_set(GPIO_NRF_CS, 1);
+
+    for (;;) {
+        acc_read_xyz(&pos_vector);
+        gpio_set(GPIO_NRF_CS, 0);
+        status_t ret = HAL_SPI_Transmit(&spi_handle, (uint8_t *)&pos_vector, sizeof(pos_vector), 5000);
+        if (ret != NO_ERROR) {
+            printf("error on spi_write for sensors: %d\n", ret);
+        }
+        gpio_set(GPIO_NRF_CS, 1);
+        thread_sleep(100);
+    }
+}
+
+APP_START(sbb)
+    .init  = nrf_sensors_init,
+    .entry = nrf_sensors_entry,
+APP_END

app/nrf_sensors/rules.mk

@@ -0,0 +1,9 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+MODULE := $(LOCAL_DIR)
+
+MODULE_SRCS += \
+	$(LOCAL_DIR)/nrf_sensors.c \
+
+
+include make/module.mk

external/platform/stm32f7xx/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.c

@@ -509,6 +509,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
   * @param  Timeout: Timeout duration
   * @retval HAL status
   */
+#include <stdio.h>
+#include <trace.h>
 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
     __IO uint16_t tmpreg;
@@ -527,9 +529,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
         return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
     }
 
+    TRACE;
     /* Process Locked */
     __HAL_LOCK(hspi);
 
+    TRACE;
+
     hspi->State       = HAL_SPI_STATE_BUSY_RX;
     hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
     hspi->pRxBuffPtr  = pData;
@@ -546,6 +551,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
         hspi->RxXferCount--;
     }
 
+
+    TRACE;
+
     /* Set the Rx Fido threshold */
     if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) {
         /* set fiforxthreshold according the reception data length: 16bit */
@@ -555,20 +563,35 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
         SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
     }
 
+
+    TRACE;
+
     /* Configure communication direction 1Line and enabled SPI if needed */
     if (hspi->Init.Direction == SPI_DIRECTION_1LINE) {
         SPI_1LINE_RX(hspi);
     }
 
+
+    TRACE;
+
     /* Check if the SPI is already enabled */
     if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) {
         /* Enable SPI peripheral */
         __HAL_SPI_ENABLE(hspi);
     }
 
+
+    TRACE;
+
     /* Receive data in 8 Bit mode */
     if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) {
+
+    TRACE;
+
         while (hspi->RxXferCount > 1) {
+
+    TRACE;
+
             /* Wait until the RXNE flag */
             if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) {
                 return HAL_TIMEOUT;
@@ -588,6 +611,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
         }
     }
 
+
+    TRACE;
+
     /* Enable CRC Transmission */
     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) {
         hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
@@ -598,6 +624,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
         return HAL_TIMEOUT;
     }
 
+
+    TRACE;
+
     /* Receive last data in 16 Bit mode */
     if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) {
         *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;

include/dev/accelerometer.h

@@ -23,9 +23,9 @@
 #ifndef __DEV_ACCELEROMETER_H
 #define __DEV_ACCELEROMETER_H
 typedef struct {
-    double x;
-    double y;
-    double z;
+    float x;
+    float y;
+    float z;
 } position_vector_t;
 
 status_t acc_read_xyz(position_vector_t *pos_vector);

platform/stm32f7xx/gpio.c

@@ -158,3 +158,42 @@ int gpio_get(unsigned nr)
     return HAL_GPIO_ReadPin(port_to_pointer(GPIO_PORT(nr)), 1 << GPIO_PIN(nr));
 }
 
+#ifdef WITH_LIB_CONSOLE
+#include <ctype.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <lib/console.h>
+
+static int cmd_stgpio(int argc, const cmd_args *argv)
+{
+    if (argc >= 3) {
+        char port = toupper(argv[2].str[0]);
+        int pin = atoi(&argv[2].str[1]);
+        uint32_t nr = ((port - 'A') << 8) | (pin & 0xff);
+
+        if (argc == 4 && !strcmp(argv[1].str,"set")) {
+            unsigned int value = argv[3].u;
+
+            gpio_set(nr, value);
+            return 0;
+        } else if (argc == 3 && !strcmp(argv[1].str,"get")) {
+            printf("gpio %c%d: %d\n", port, pin, gpio_get(nr));
+            return 0;
+        } else {
+            goto print_usage;
+        }
+    }
+
+print_usage:
+    printf("stgpio set <gpio [A-K][0-15]> <value>\n");
+    printf("stgpio get <gpio [A-K][0-15]>\n");
+    putchar('\n');
+
+    return 0;
+}
+STATIC_COMMAND_START
+STATIC_COMMAND("stgpio", "wrapper for gpio commands with ST gpio naming conventions of [A-K][1-15]", &cmd_stgpio)
+STATIC_COMMAND_END(stgpio);
+
+#endif

platform/stm32f7xx/include/platform/spi.h

@@ -0,0 +1,274 @@
+#pragma once
+#include <err.h>
+#include <compiler.h>
+#include <platform/stm32.h>
+#include <kernel/mutex.h>
+
+struct spi_bus {
+    SPI_TypeDef *spi;
+    mutex_t lock;
+};
+
+#define INVALID_SPI_BUS -1
+
+status_t spi_init(SPI_HandleTypeDef *handle);
+status_t spi_write(SPI_HandleTypeDef *handle, uint8_t *data, size_t len, uint32_t cs);
+status_t spi_read(SPI_HandleTypeDef *handle, uint8_t *data, size_t len, uint32_t cs);
+status_t spi_transaction(SPI_HandleTypeDef *handle, uint8_t *wdata, uint8_t *rdata, size_t len, uint32_t cs);
+
+// Structure definitions for the STM32F7 spi controller. The intention is to point stm32f7_spi_t
+// at one of the spi base addresses defines such as SPI1
+//
+// ex: volatile stm32f7_spi_t *spi2 = (stm32f7_spi_t *) SPI2;
+
+typedef struct {
+    uint16_t cpha:1;
+    uint16_t cpol:1;
+    uint16_t mstr:1;
+    uint16_t br:3;
+    uint16_t spe:1;
+    uint16_t lsb_first:1;
+    uint16_t ssi:1;
+    uint16_t ssm:1;
+    uint16_t rx_only:1;
+    uint16_t crcl:1;
+    uint16_t crc_next:1;
+    uint16_t crc_en:1;
+    uint16_t bidi_oe:1;
+    uint16_t bidi_mode:1;
+} SPIx_CR1_t;
+
+typedef struct {
+    uint16_t rxdmaen:1;
+    uint16_t txdmaen:1;
+    uint16_t ssoe:1;
+    uint16_t nssp:1;
+    uint16_t frf:1;
+    uint16_t errie:1;
+    uint16_t rxneie:1;
+    uint16_t txeie:1;
+    uint16_t ds:4;
+    uint16_t frxth:1;
+    uint16_t ldma_rx:1;
+    uint16_t ldma_tx:1;
+    uint16_t __reserved0:1;
+} SPIx_CR2_t;
+
+typedef struct {
+    uint16_t rxne:1;
+    uint16_t txe:1;
+    uint16_t chside:1;
+    uint16_t udr:1;
+    uint16_t crcerr:1;
+    uint16_t modf:1;
+    uint16_t ovr:1;
+    uint16_t bsy:1;
+    uint16_t fre:1;
+    uint16_t frlvl:2;
+    uint16_t ftlvl:2;
+    uint16_t __reserved0:3;
+} SPIx_SR_t;
+
+typedef struct {
+    SPIx_CR1_t CR1;
+    uint16_t __reserved0;
+    SPIx_CR2_t CR2;
+    uint16_t __reserved1;
+    SPIx_SR_t SR;
+    uint16_t __reserved2;
+    uint16_t DR;
+} stm32f7_spi_t;
+
+enum cpha {
+    cpha_first_transition  = 0x0,
+    cpha_second_transition = 0x1,
+};
+
+enum cpol {
+    cpol_clk_idle_low  = 0x0,
+    cpol_clk_idle_high = 0x1,
+};
+
+enum mstr {
+    mstr_spi_slave  = 0x0,
+    mstr_spi_master = 0x1,
+};
+
+enum br {
+    fpclk_div_2   = 0b000,
+    fpclk_div_4   = 0b001,
+    fpclk_div_8   = 0b010,
+    fpclk_div_16  = 0b011,
+    fpclk_div_32  = 0b100,
+    fpclk_div_64  = 0b101,
+    fpclk_div_128 = 0b110,
+    fpclk_div_256 = 0b111,
+};
+
+enum spe {
+    spe_spi_disable = 0x0,
+    spe_spi_enabled = 0x1,
+};
+
+enum ssm {
+    ssm_disabled = 0x0,
+    ssm_enabled  = 0x1,
+};
+
+enum rxonly {
+    rxonly_full_duplex     = 0x0,
+    rxonly_output_disabled = 0x1,
+};
+
+enum crcl {
+    crcl_8bit  = 0x0,
+    crcl_16bit = 0x1,
+};
+
+enum crcnext {
+    crcnext_tx_buf_next = 0x0,
+    crcnext_tx_crc_next = 0x1,
+};
+
+enum crcen {
+    hw_crc_disable = 0x0,
+    hw_crc_enable  = 0x1,
+};
+
+enum bidioe {
+    bidi_output_disable = 0x0,
+    bidi_output_enable  = 0x1,
+};
+
+enum bidimode {
+    bidi_mode_2 = 0x0,
+    bidi_mode_1 = 0x1,
+};
+
+enum rxdmaen {
+    rx_dma_disabled = 0x0,
+    rx_dma_enabled  = 0x1,
+};
+
+enum txdmaen {
+    tx_dma_disabled = 0x0,
+    tx_dma_enabled  = 0x1,
+};
+
+enum ssoe {
+    ss_output_disabled = 0x0,
+    ss_output_enabled  = 0x1,
+};
+
+enum nssp {
+    nss_pulse_disable = 0x0,
+    nss_pulse_enable  = 0x1,
+};
+
+enum frf {
+    motorola_mode = 0x0,
+    ti_mode       = 0x1,
+};
+
+enum errie {
+    err_int_mask   = 0x0,
+    err_int_enable = 0x1,
+};
+
+enum rxneie {
+    rxne_int_mask   = 0x0,
+    rxne_int_enable = 0x1,
+};
+
+enum txeie {
+    txe_int_mask   = 0x0,
+    txe_int_enable = 0x1,
+};
+
+enum ds {
+    data_size_4bit  = 0b0011,
+    data_size_5bit  = 0b0100,
+    data_size_6bit  = 0b0101,
+    data_size_7bit  = 0b0110,
+    data_size_8bit  = 0b0111,
+    data_size_9bit  = 0b1000,
+    data_size_10bit = 0b1001,
+    data_size_11bit = 0b1010,
+    data_size_12bit = 0b1011,
+    data_size_13bit = 0b1100,
+    data_size_14bit = 0b1101,
+    data_size_15bit = 0b1110,
+    data_size_16bit = 0b1111,
+};
+
+enum frxth {
+    rxne_event_fifo_1_2 = 0x0,
+    rxne_event_fifo_1_4 = 0x1,
+};
+
+enum ldma_rx {
+    data_rx_even = 0x0,
+    data_rx_odd  = 0x1,
+};
+
+enum ldma_tx {
+    data_tx_even = 0x0,
+    data_tx_odd  = 0x1,
+};
+
+enum sr_rxne {
+    sr_rx_buf_empty     = 0x0,
+    sr_rx_buf_not_empty = 0x1,
+};
+
+enum sr_txne {
+    sr_tx_buf_empty     = 0x0,
+    sr_tx_buf_not_empty = 0x1,
+};
+
+// CHSIDE unused in SPI mode
+// UDR unused in SPI mode
+
+enum crcerr {
+    sr_crc_match    = 0x0,
+    sr_crc_mismatch = 0x1,
+};
+
+enum modf {
+    sr_mode_fault    = 0x0,
+    sr_no_mode_fault = 0x1,
+};
+
+enum ovr {
+    sr_no_overrun = 0x0,
+    sr_overrun    = 0x1,
+};
+
+enum bsy {
+    sr_not_busy   = 0x0,
+    sr_busy       = 0x1,
+};
+
+enum fre {
+    sr_no_fre = 0x0,
+    sr_fre    = 0x1,
+};
+
+enum frlvl {
+    sr_rx_fifo_empty = 0b00,
+    sr_rx_fifo_1_4   = 0b01,
+    sr_rx_fifo_1_2   = 0b10,
+    sr_rx_fifo_full  = 0b11,
+};
+
+enum ftlvl {
+    sr_tx_fifo_empty = 0b00,
+    sr_tx_fifo_1_4   = 0b01,
+    sr_tx_fifo_1_2   = 0b10,
+    sr_tx_fifo_full  = 0b11,
+};
+
+STATIC_ASSERT(__builtin_offsetof(stm32f7_spi_t, CR1) == 0x0);
+STATIC_ASSERT(__builtin_offsetof(stm32f7_spi_t, CR2) == 0x4);
+STATIC_ASSERT(__builtin_offsetof(stm32f7_spi_t, SR) == 0x8);
+STATIC_ASSERT(__builtin_offsetof(stm32f7_spi_t, DR) == 0xC);

platform/stm32f7xx/rules.mk

@@ -48,11 +48,12 @@ MODULE_SRCS += \
 	$(LOCAL_DIR)/usbc.c \
 	$(LOCAL_DIR)/vectab.c \
 	$(LOCAL_DIR)/sdram.c \
+	$(LOCAL_DIR)/spi.c \
 	$(LOCAL_DIR)/qspi.c
 
-# use a two segment memory layout, where all of the read-only sections 
-# of the binary reside in rom, and the read/write are in memory. The 
-# ROMBASE, MEMBASE, and MEMSIZE make variables are required to be set 
+# use a two segment memory layout, where all of the read-only sections
+# of the binary reside in rom, and the read/write are in memory. The
+# ROMBASE, MEMBASE, and MEMSIZE make variables are required to be set
 # for the linker script to be generated properly.
 #
 LINKER_SCRIPT += \

platform/stm32f7xx/spi.c

@@ -0,0 +1,317 @@
+#include <assert.h>
+#include <debug.h>
+#include <stdlib.h>
+#include <string.h>
+#include <target/gpioconfig.h>
+#include <platform/spi.h>
+#include <platform/stm32.h>
+
+static struct spi_bus spi_busses[] = {
+    { .spi = SPI1 },
+    { .spi = SPI2 },
+    { .spi = SPI3 },
+    { .spi = SPI4 },
+    { .spi = SPI5 },
+    { .spi = SPI6 }
+};
+
+static inline int get_bus_idx(SPI_TypeDef *spi)
+{
+    for (unsigned int i = 0; i < (sizeof(spi_busses)/sizeof(spi_busses[0])); i++) {
+        if (spi_busses[i].spi == spi) {
+            return i;
+        }
+    }
+
+    return INVALID_SPI_BUS;
+}
+
+static bool wait_for_bus_ready(SPI_HandleTypeDef *handle)
+{
+    size_t timeout = 1024;
+    while (timeout && (HAL_SPI_GetState(handle) != HAL_SPI_STATE_READY)) {
+        timeout--;
+    }
+
+    if (timeout == 0) {
+        return false;
+    }
+
+    return true;
+}
+
+status_t spi_init (SPI_HandleTypeDef *handle)
+{
+    DEBUG_ASSERT(handle);
+
+    status_t ret = NO_ERROR;
+    int bus = get_bus_idx(handle->Instance);
+
+    if (bus == INVALID_SPI_BUS) {
+        return ERR_NOT_FOUND;
+    }
+
+    mutex_init(&(spi_busses[bus].lock));
+    if (HAL_SPI_Init(handle) != HAL_OK) {
+        ret = ERR_GENERIC;
+    }
+
+    return ret;
+}
+
+status_t spi_write(SPI_HandleTypeDef *handle, uint8_t *data, size_t len, uint32_t cs)
+{
+    DEBUG_ASSERT(handle);
+    DEBUG_ASSERT(data);
+    DEBUG_ASSERT(len);
+
+    status_t ret = NO_ERROR;
+    int bus = get_bus_idx(handle->Instance);
+    int cs_val = 0;
+    bool use_soft_nss = ((handle->Init.NSS == SPI_NSS_SOFT) && cs);
+
+    if (bus == INVALID_SPI_BUS) {
+        return ERR_NOT_FOUND;
+    }
+
+    mutex_acquire(&(spi_busses[bus].lock));
+    if (use_soft_nss) {
+        cs_val = gpio_get(cs);
+        gpio_set(cs, !cs_val);
+    }
+
+    HAL_StatusTypeDef foo;
+
+    /* The lock may have been released while the hardware is still processing a transaction */
+    if (!wait_for_bus_ready(handle)) {
+        ret = ERR_BUSY;
+    } else {
+        if ((foo = HAL_SPI_Transmit(handle, data, len, HAL_MAX_DELAY)) != HAL_OK) {
+            ret = ERR_IO;
+        }
+    }
+
+    if (use_soft_nss) {
+        gpio_set(cs, cs_val);
+    }
+    mutex_release(&(spi_busses[bus].lock));
+
+    return ret;
+}
+
+status_t spi_read(SPI_HandleTypeDef *handle, uint8_t *data, size_t len, uint32_t cs)
+{
+    DEBUG_ASSERT(handle);
+    DEBUG_ASSERT(data);
+    DEBUG_ASSERT(len);
+
+    status_t ret = NO_ERROR;
+    int bus = get_bus_idx(handle->Instance);
+    int cs_val;
+    bool use_soft_nss = (handle->Init.NSS == SPI_NSS_SOFT);
+
+    if (bus == INVALID_SPI_BUS) {
+        return ERR_NOT_FOUND;
+    }
+
+    mutex_acquire(&(spi_busses[bus].lock));
+    if (use_soft_nss) {
+        cs_val = gpio_get(cs);
+        gpio_set(cs, !cs_val);
+    }
+
+    if (HAL_SPI_Receive(handle, data, len, HAL_MAX_DELAY) != HAL_OK) {
+        ret = ERR_IO;
+    }
+
+    if (use_soft_nss) {
+        gpio_set(cs, cs_val);
+    }
+    mutex_release(&(spi_busses[bus].lock));
+
+    return ret;
+}
+
+status_t spi_transaction(SPI_HandleTypeDef *handle, uint8_t *wdata, uint8_t *rdata, size_t len, uint32_t cs)
+{
+    DEBUG_ASSERT(handle);
+    DEBUG_ASSERT(wdata);
+    DEBUG_ASSERT(rdata);
+    DEBUG_ASSERT(len);
+
+    status_t ret = NO_ERROR;
+    int bus = get_bus_idx(handle->Instance);
+
+    if (bus == INVALID_SPI_BUS) {
+        return ERR_NOT_FOUND;
+    }
+
+    mutex_acquire(&(spi_busses[bus].lock));
+    if (handle->Init.NSS == SPI_NSS_SOFT) {
+        gpio_set(cs, (handle->Init.CLKPolarity == 0) ? GPIO_PIN_RESET : GPIO_PIN_SET);
+    }
+
+    if (HAL_SPI_TransmitReceive(handle, wdata, rdata, len, HAL_MAX_DELAY) != HAL_OK) {
+        ret = ERR_IO;
+    }
+
+    if (handle->Init.NSS == SPI_NSS_SOFT) {
+        gpio_set(cs, (handle->Init.CLKPolarity == 0) ? GPIO_PIN_SET : GPIO_PIN_RESET);
+    }
+    mutex_release(&(spi_busses[bus].lock));
+
+    return ret;
+}
+
+#if WITH_LIB_CONSOLE
+#include <lib/console.h>
+
+/* Bus configurations for testing. Although it requires a recompilation per setting tweaked,
+ * it saves us from having to write a great deal of configuration code via an awkward console
+ * interface with many arguments.
+ *
+ * XXX: This doesn't handle soft NSS on its own.
+ */
+
+// This test code is primarily for DartuinoP0 and the GPIO will only exist for that target
+#define STM32F7_SPI_BUS_CNT     6
+static SPI_HandleTypeDef handles[STM32F7_SPI_BUS_CNT] = {
+    [0] = { 0 },
+    [1] = {
+        .Instance               = SPI2,
+        .Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4,
+        .Init.Direction         = SPI_DIRECTION_1LINE,
+        .Init.CLKPhase          = SPI_PHASE_1EDGE,
+        .Init.CLKPolarity       = SPI_POLARITY_LOW,
+        .Init.DataSize          = SPI_DATASIZE_8BIT,
+        .Init.FirstBit          = SPI_FIRSTBIT_LSB,
+        .Init.TIMode            = SPI_TIMODE_DISABLE,
+        .Init.CRCCalculation    = SPI_CRCCALCULATION_DISABLE,
+        .Init.CRCPolynomial     = 7,
+        .Init.NSS               = SPI_NSS_SOFT,
+        .Init.Mode              = SPI_MODE_MASTER,
+    },
+    [2] = { 0 },
+    [3] = { 0 },
+    [4] = { 0 },
+    [5] = {
+        .Instance               = SPI5,
+        .Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4,
+        .Init.Direction         = SPI_DIRECTION_1LINE,
+        .Init.CLKPhase          = SPI_PHASE_1EDGE,
+        .Init.CLKPolarity       = SPI_POLARITY_LOW,
+        .Init.DataSize          = SPI_DATASIZE_8BIT,
+        .Init.FirstBit          = SPI_FIRSTBIT_MSB,
+        .Init.TIMode            = SPI_TIMODE_DISABLE,
+        .Init.CRCCalculation    = SPI_CRCCALCULATION_DISABLE,
+        .Init.CRCPolynomial     = 7,
+        .Init.NSS               = SPI_NSS_SOFT,
+        .Init.Mode              = SPI_MODE_MASTER,
+    },
+};
+
+// GPIO to whack for soft chip select
+static unsigned int handle_nss[STM32F7_SPI_BUS_CNT] = {
+    [5] = GPIO(GPIO_PORT_K, 0), // NRF_CS on Dartuino P0
+};
+
+
+/* Check if bus is valid, initialize it if needed */
+static inline bool check_bus(uint8_t bus)
+{
+    if (bus < STM32F7_SPI_BUS_CNT && handles[bus].Instance == 0) {
+        return false;
+    }
+
+    if (HAL_SPI_GetState(&handles[bus]) == HAL_SPI_STATE_RESET) {
+        HAL_SPI_Init(&handles[bus]);
+    }
+
+    return true;
+}
+
+static void print_spi_usage(void)
+{
+    printf("spi read <bus> <len>\n");
+    printf("\tRead <len> bytes from <bus>\n");
+    printf("spi spew <bus> <len> <n> <delay>\n");
+    printf("\tWrite <len> bytes <n> times with a delay of <delay> ms between over <bus>\n");
+}
+
+#define IS_CMD(_str, _argc) (argc >= _argc && (strcmp(_str, argv[1].str) == 0))
+static int cmd_spi(int argc, const cmd_args *argv)
+{
+    status_t ret = NO_ERROR;
+    // spi read <bus> <len>
+    if (IS_CMD("read", 4)) {
+        uint8_t bus = argv[2].i;
+        size_t len = MIN(1024, argv[3].i);
+        uint8_t *data = (uint8_t *)malloc(len);
+
+        if (!data) {
+            ret = ERR_NO_MEMORY;
+            goto read_err;
+        }
+
+        if (!check_bus(bus)) {
+            printf("Error: bus %u is invalid\n", bus);
+            ret = ERR_INVALID_ARGS;
+            goto read_err;
+        }
+
+        if (spi_read(&handles[bus], data, len, handle_nss[bus]) != NO_ERROR) {
+            printf("spi read error\n");
+            ret = ERR_IO;
+            goto read_err;
+        }
+
+        hexdump8(data, len);
+
+read_err:
+        free(data);
+
+    // spi spew <bus> <len> <iterations> <delay>
+    } else if (IS_CMD("spew", 6)) {
+        uint8_t bus = argv[2].i;
+        size_t len = MIN(1024, argv[3].i);
+        uint32_t cnt = argv[4].i;
+        uint32_t delay = argv[5].i;
+        uint8_t *data = (uint8_t *)malloc(len);
+
+        if (cnt == 0) {
+            cnt = UINT32_MAX;
+        }
+
+        for (uint32_t i = 0; i < len; i++) {
+            data[i] = i % 255;
+        }
+
+        for (uint32_t i = 0; i < cnt; i++) {
+            int spi_ret;
+            if ((spi_ret = spi_write(&handles[bus], data, len, handle_nss[bus])) != NO_ERROR) {
+                printf("spi write error: %d\n", spi_ret);
+                ret = ERR_IO;
+                goto spew_err;
+            }
+
+            if (delay > 0) {
+                thread_sleep(delay);
+            }
+        }
+
+spew_err:
+        free(data);
+    } else {
+        print_spi_usage();
+    }
+
+    return ret;
+}
+
+STATIC_COMMAND_START
+STATIC_COMMAND("spi", "spi commands for stm32f7", &cmd_spi)
+STATIC_COMMAND_END(spi);
+
+
+
+#endif // WITH_LIB_CONSOLE

project/dartuinoP0-test.mk

@@ -13,6 +13,7 @@ MODULES += \
 
 MODULE_DEPS += \
     app/accelerometer \
+	app/nrf_sensors \
 
 MODULE_SRCS += \
     $(LOCAL_DIR)/sensor_bus.c \

scripts/do-dartuinoP0-test

@@ -3,5 +3,5 @@
 export PROJECT=dartuinoP0-test
 
 make -j8 &&
-openocd -f interface/stlink-v2.cfg -f board/stm32756g_eval.cfg \
+openocd -f interface/stlink-v2.cfg -f target/stm32f7x.cfg \
     -c "program build-$PROJECT/lk.bin reset exit 0x08000000"

scripts/do-stm32f7-disco-test

@@ -3,5 +3,5 @@
 export PROJECT=stm32f746g-disco-test
 
 make -j8 &&
-openocd -f interface/stlink-v2-1.cfg -f board/stm32756g_eval.cfg \
+openocd -f interface/stlink-v2-1.cfg -f board/stm32f7discovery.cfg \
     -c "program build-$PROJECT/lk.bin reset exit 0x08000000"

target/dartuinoP0/display/et011tt2v1.h

@@ -0,0 +1,308 @@
+
+
+
+typedef struct {
+    // Gate power selection
+    // 0: External gate power from VGH/VGL pins
+    // 1: Internal DC/DC function for generating VGH/VGL
+    uint8_t vg_en:1;
+    // Source power selection
+    // 0: External source power from VDH/VDL pins
+    // 1: Internal DC/DC function for generating VDH/VDL
+    uint8_t vs_en:1;
+    uint8_t __rs0:6;
+    //---- new byte
+    // VG_LVL[1:0]: Gate Voltage Level selection
+    //  Bit definitions in power settings enum.
+    uint8_t vg_lvl:2;
+    // VCOM_HV: VCOM Voltage Level
+    //  0: VCOMH=VSH+VCOMDC, VCOML=VSL+VCOMDC (default)
+    //  1: VCOML=VGH, VCOML=VGL
+    uint8_t vcom_hv:1;
+    uint8_t __rs1:5;
+    //---- new byte
+    // VSH_LVL[5:0]: Internal positive source voltage level for K/W
+    // (range: +2.4V ~ +11.0V / step:0.2V / default : +10.0V)
+    uint8_t vsh_lvl:6;
+    uint8_t __rs2:2;
+    //---- new byte
+    // VSL_LVL[5:0]: Internal negative source voltage level for K/W
+    // (range: -2.4V ~ -11.0V / step:0.2V / default : -10.0V)
+    uint8_t vsl_lvl:6;
+    uint8_t __rs3:2;
+    //---- new byte
+    uint8_t vshr_lvl:6;
+    uint8_t __rs4:2;
+} pwr_settings_t;
+
+typedef struct {
+    uint8_t btpha_min_off:3;
+    uint8_t btpha_drive_strength:3;
+    uint8_t btpha_soft_start:2;
+    //---- new byte
+    uint8_t btphb_min_off:3;
+    uint8_t btphb_drive_strength:3;
+    uint8_t btphb_soft_start:2;
+    //---- new byte
+    uint8_t btphc_min_off:3;
+    uint8_t btphc_drive_strength:3;
+} booster_settings_t;
+
+typedef struct {
+    uint8_t busy_n:1;
+    uint8_t pof:1;
+    uint8_t pon:1;
+    uint8_t data_flag:1;
+    uint8_t i2c_busyn:1;
+    uint8_t i2c_err:1;
+    uint8_t __rs0:2;
+} et011tt2_status_t;
+
+typedef struct {
+    // DDX[1:0]: Data polarity
+    //  0: Inverted
+    //  1: Normal (default)
+    uint8_t ddx:1;
+    uint8_t __rs0:3;
+    // VBD[1:0]: Border output selection
+    uint8_t bdd:2;
+    // BDV: Border DC Voltage control
+    //  0: Border Output DC Voltage Function disabled (default)
+    //  1: Border Output DC Voltage Function enabled
+    uint8_t bdv:1;
+    // BDZ: Border Hi-Z control
+    //  0: Border Output Hi-Z disabled (default)
+    //  1: Border Output Hi-Z enabled
+    uint8_t bdz:1;
+    //---- new byte
+    // CDI[9:0]: VCOM to Source interval. Interval time setting from VCOM to
+    // source dat.
+    //  000 0000 000b ~ 11 1111 1111b: 1 Hsync ~ 1023 Hsync, respectively.
+    //  (Default: 018h: 25 Hsync)
+    uint8_t cdi_high:2;
+    uint8_t __rs1:2;
+    // DCI[3:0]: Source to VCOM interval. Interval time setting from source
+    // data to VCOM.
+    //  0000b ~ 1111b: 1 Hsync ~ 16 Hsync, respectively. (Default: 011b: 4
+    //  Hsync)
+    uint8_t dci:4;
+    //---- new byte
+    uint8_t cdi_low;
+} vcom_data_int_settings_t;
+
+typedef struct {
+    uint8_t __rs0:2;
+    // HRES[7:2]: Horizontal display resolution.
+    //  00000b ~ 11111b: 4 ~ 256 lines
+    uint8_t hres:6;
+    //---- new byte
+    // VRES[9:0]: Vertical display resolution
+    //  0000000000b ~ 1111111111b: 1 ~ 1024 lines
+    uint8_t vres_high:2;
+    uint8_t __rs1:6;
+    //---- new byte
+    uint8_t vres_low;
+} resolution_settings_t;
+
+typedef struct {
+    // G1~4NUM[3:0]: Channel Number used for Gate Group 1~4. For example:
+    //  2: GGx[2:0] ON
+    //  15: GGx[15:0] ON
+    uint8_t g1num:4;
+    uint8_t __rs0:1;
+    // G1~4UD: Gate Group 1~4 Up/Down Selection
+    //  0: Down scan within Gate Group
+    //  1: Up scan within Gate Group (default)
+    uint8_t g1ud:1;
+    // G1~4BS: Gate Group 1~4 Block/Select Selection
+    //  0: Gate Select
+    //  1: Gate Block
+    uint8_t g1bs:1;
+    // G1~4EN: Gate Group 1~4 Enable
+    //  0: Disable
+    //  1: Enable
+    uint8_t g1en:1;
+    //---- new byte
+    uint8_t g2num:4;
+    uint8_t __rs1:1;
+    uint8_t g2ud:1;
+    uint8_t g2bs:1;
+    uint8_t g2en:1;
+    //---- new byte
+    uint8_t g3num:4;
+    uint8_t __rs2:1;
+    uint8_t g3ud:1;
+    uint8_t g3bs:1;
+    uint8_t g3en:1;
+    //---- new byte
+    uint8_t g4num:4;
+    uint8_t __rs3:1;
+    uint8_t g4ud:1;
+    uint8_t g4bs:1;
+    uint8_t g4en:1;
+    //---- new byte
+    // GSFB: Gate Select Forward/Backward
+    //  0: Gate select backward
+    //  1: Gate select forward
+    uint8_t gsfb:1;
+    // GBFB: Gate Block Forward/Backward
+    //  0: Gate block backward
+    //  1: Gate block forward
+    uint8_t gbfb:1;
+    uint8_t __rs4:2;
+    // XOPT: XON Option
+    //  0: No all gate on during vertical blanking in XON mode (default)
+    //  1: All gate on during vertical blanking in XON mode
+    uint8_t xopt:1;
+    uint8_t __rs5:3;
+} gate_group_settings_t;
+
+typedef struct {
+    uint8_t vbds:7;
+    uint8_t __rs0:1;
+} border_dc_v_settings_t;
+
+typedef struct {
+    // Low Power Voltage Selection
+    uint8_t lpd_sel:2;
+    uint8_t __rs0:6;
+} lpdselect_t;
+
+typedef struct {
+    uint8_t pixel3:2;
+    uint8_t pixel2:2;
+    uint8_t pixel1:2;
+    uint8_t pixel0:2;
+} data_tranmission_t;
+
+typedef struct {
+    // X[7:0]: X-axis Start Point. X-axis start point for update display window.
+    // NOTE: The X-axis start point needs to be a multiple of 4.
+    uint8_t x;
+    // Y[9:0]: Y-axis Start Point. Y-axis start point for update display window.
+    uint8_t y_high:2;
+    uint8_t __rs0:6;
+    uint8_t y_low;
+    // W[7:0]: X-axis Window Width. X-axis width for update display window.
+    // NOTE: The width needs to be a multiple of 4.
+    // NOTE: This needs to be set to W - 1.
+    uint8_t w;
+    uint8_t l_high:2;
+    uint8_t __rs1:6;
+    // L[9:0]: Y-axis Window Width. Y-axis width for update display window
+    // NOTE: This needs to be set to L - 1.
+    uint8_t l_low;
+} data_transmission_window_t;
+
+typedef struct {
+    uint8_t mode:2;
+    // DN_EN: Do-nothing function enabled
+    //  0: Data follow VCOM function disable
+    //  1: Data output follows VCOM LUT if new pixel data equal to old pixel
+    //     data inside Update Display Area
+    // NOTE: Do-nothing function is always active outside Update Display Area.
+    uint8_t dn_en:1;
+    // RGL_EN: REGAL function control
+    //  0: REGAL function disable
+    //  1: REGAL function enable
+    uint8_t rgl_en:1;
+    // PSCAN: Partial Scan control
+    //  0: Partial Scan disable
+    //  1: Partial Scan enable (Gate Scan within Display Window only)
+    uint8_t pscan:1;
+    uint8_t __rs0:3;
+    //---- new byte
+    // X[7:0]: X-axis Start Point. X-axis start point for update display window.
+    // NOTE: The X-axis start point needs to be a multiple of 4.
+    uint8_t x;
+    // Y[9:0]: Y-axis Start Point. Y-axis start point for update display window.
+    uint8_t y_high:2;
+    uint8_t __rs1:6;
+    //---- new byte
+    uint8_t y_low;
+    // W[7:0]: X-axis Window Width. X-axis width for update display window.
+    // NOTE: The width needs to be a multiple of 4.
+    // NOTE: This needs to be set to W - 1.
+    uint8_t w;
+    // L[9:0]: Y-axis Window Width. Y-axis width for update display window
+    // NOTE: This needs to be set to L - 1.
+    uint8_t l_high:2;
+    uint8_t __rs2:6;
+    uint8_t l_low;
+} display_refresh_t;
+
+enum {
+    PanelSetting                = 0x00,
+    PowerSetting                = 0x01,
+    PowerOff                    = 0x02,
+    PowerOffSequenceSetting     = 0x03,
+    PowerOn                     = 0x04,
+    BoosterSoftStart            = 0x06,
+    DeepSleep                   = 0x07,
+    DisplayRefresh              = 0x12,
+    DataStartTransmission2      = 0x13,
+    DataStartTransmissionWindow = 0x14,
+    KwgVcomLutRegister          = 0x20,
+    KwgLutRegister              = 0x22,
+    FtLutRegister               = 0x26,
+    PllControl                  = 0x30,
+    TemperatureSensor           = 0x40,
+    TemperatureSensorEnable     = 0x41,
+    TemperatureSensorWrite      = 0x42,
+    TemperatureSensorRead       = 0x43,
+    VcomAndDataIntervalSetting  = 0x50,
+    LowPowerDetection           = 0x51,
+    ResolutionSetting           = 0x61,
+    GateGroupSetting            = 0x62,
+    GateBlockSetting            = 0x63,
+    GateSelectSetting           = 0x64,
+    Revision                    = 0x70,
+    GetStatus                   = 0x71,
+    AutoMeasureVcom             = 0x80,
+    VcomValue                   = 0x81,
+    VcomDcSetting               = 0x82,
+    BorderDcVoltageSetting      = 0x84,
+    LpdSelect                   = 0xE4,
+  };
+
+
+enum booster_soft_start_min_off {
+    soft_start_min_off_0p27us = 0b000,
+    soft_start_min_off_0p34us = 0b001,
+    soft_start_min_off_0p40us = 0b010,
+    soft_start_min_off_0p50us = 0b011,
+    soft_start_min_off_0p80us = 0b100,
+    soft_start_min_off_1p54us = 0b101,
+    soft_start_min_off_3p34us = 0b110,
+    soft_start_min_off_6p58us = 0b111,
+};
+
+enum drive_strength {
+    drive_strength_1 = 0b000,
+    drive_strength_2 = 0b001,
+    drive_strength_3 = 0b010,
+    drive_strength_4 = 0b011,
+    drive_strength_5 = 0b100,
+    drive_strength_6 = 0b101,
+    drive_strength_7 = 0b110,
+    drive_strength_8 = 0b111,  // (strongest)
+};
+
+enum soft_start_period {
+    soft_start_period_10ms = 0b00,
+    soft_start_period_20ms = 0b01,
+    soft_start_period_30ms = 0b10,
+    soft_start_period_40ms = 0b11,
+};
+
+enum lpd_select_lpdsel {
+    LPDSEL_2p2v = 0b00,
+    LPDSEL_2p3v = 0b01,
+    LPDSEL_2p4v = 0b10,
+    LPDSEL_2p5v = 0b11, // (default)
+};
+
+#define PHYSICAL_WIDTH  240
+#define PHYSICAL_HEIGHT 240
+#define EINK_WHITE      0xFF
+#define EINK_BLACK      0x00

target/dartuinoP0/include/target/et011tt2v1.h

@@ -0,0 +1,10 @@
+
+
+
+#define FBSIZE  240*240>>2
+
+
+int eink_refresh(void);
+status_t eink_init(void);
+
+uint8_t * get_eink_framebuffer(void);        // returns pointer to eink framebuffer

target/dartuinoP0/include/target/gpioconfig.h

@@ -78,16 +78,26 @@
             __HAL_RCC_GPIOK_CLK_ENABLE(); \
             __HAL_RCC_GPIOF_CLK_ENABLE()
 
+#define GPIO_NRF_RST        GPIO(GPIO_PORT_A, 13)
+#define GPIO_NRF_SWDIO      GPIO(GPIO_PORT_A, 13)
+#define GPIO_NRF_SWCLK      GPIO(GPIO_PORT_A, 14)
 #define GPIO_NRF_CS         GPIO(GPIO_PORT_K, 0)
 #define GPIO_NRF_INT        GPIO(GPIO_PORT_K, 1)
 #define GPIO_GYRO_nCS       GPIO(GPIO_PORT_K, 4)
 #define GPIO_GYRO_INT       GPIO(GPIO_PORT_K, 5)
 #define GPIO_ACC_nCS        GPIO(GPIO_PORT_K, 2)
 #define GPIO_ACC_INT        GPIO(GPIO_PORT_K, 3)
+#define GPIO_SPI2_SCK       GPIO(GPIO_PORT_D, 3)
+#define GPIO_SPI2_MISO      GPIO(GPIO_PORT_I, 2)
+#define GPIO_SPI2_MOSI      GPIO(GPIO_PORT_B, 15)
 #define GPIO_SPI5_SCK       GPIO(GPIO_PORT_F, 7)
 #define GPIO_SPI5_MISO      GPIO(GPIO_PORT_F, 8)
 #define GPIO_SPI5_MOSI      GPIO(GPIO_PORT_F, 9)
-
-
+#define GPIO_DISP_CS        GPIO(GPIO_PORT_B, 12)
+#define GPIO_DISP_SCK       GPIO(GPIO_PORT_D, 3)
+#define GPIO_DISP_MOSI      GPIO(GPIO_PORT_B, 15)
+#define GPIO_DISP_BUSY      GPIO(GPIO_PORT_I, 4)
+#define GPIO_DISP_DC        GPIO(GPIO_PORT_I, 5)
+#define GPIO_DISP_RST       GPIO(GPIO_PORT_K, 6)
 
 #endif

target/dartuinoP0/init.c

@@ -38,6 +38,7 @@
 #include <target/bmi055.h>
 #include <target/debugconfig.h>
 #include <target/gpioconfig.h>
+#include <target/et011tt2v1.h>
 #include <reg.h>
 
 #if ENABLE_LCD
@@ -134,7 +135,7 @@ void target_init(void)
     memory_lcd_init();
 #endif
 
-#if WITH_LIB_MINIP
+#if 0 //WITH_LIB_MINIP
     uint8_t mac_addr[6];
     gen_random_mac_address(mac_addr);
     eth_init(mac_addr, PHY_KSZ8721);
@@ -167,47 +168,80 @@ void target_init(void)
 #if ENABLE_SENSORBUS
     sensor_bus_init();
 #endif
+
+    eink_init();
 }
 
 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
 {
     GPIO_InitTypeDef  GPIO_InitStruct;
     if (hspi->Instance == SPI2) {
-        /*##-1- Enable peripherals and GPIO Clocks #################################*/
-        /* Enable GPIO TX/RX clock */
-        __HAL_RCC_GPIOD_CLK_ENABLE();
-        __HAL_RCC_GPIOK_CLK_ENABLE();
+        /* SPI2
+         * PB15 MOSI
+         * PD3 SCK
+         * PB12 CS (soft)
+         */
+        printf("Configuring SPI2.\n");
         __HAL_RCC_GPIOB_CLK_ENABLE();
-        /* Enable SPI clock */
+        __HAL_RCC_GPIOD_CLK_ENABLE();
+        __HAL_RCC_GPIOI_CLK_ENABLE();
+        __HAL_RCC_GPIOK_CLK_ENABLE();
         __HAL_RCC_SPI2_CLK_ENABLE();
 
-        /*##-2- Configure peripheral GPIO ##########################################*/
-        /* SPI SCK GPIO pin configuration  */
-        GPIO_InitStruct.Pin       = GPIO_PIN_3;
+        /* Common SPI2 AF config */
         GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-        GPIO_InitStruct.Pull      = GPIO_PULLDOWN;
+        GPIO_InitStruct.Pull      = 0x2; // GPIO_PULLDOWN
         GPIO_InitStruct.Speed     = GPIO_SPEED_HIGH;
         GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
+
+        /* SPI2 MOSI GPIO pin configuration  */
+        GPIO_InitStruct.Pin       = GPIO_PIN_15;
+        HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+        /* SPI2 SCK GPIO pin configuration */
+        GPIO_InitStruct.Pin       = GPIO_PIN_3;
         HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
 
-        /* SPI MOSI GPIO pin configuration  */
-        GPIO_InitStruct.Pin = GPIO_PIN_15;
-        HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 
+        /* SPI2 CS GPIO pin configuration (general output GPIO) */
         GPIO_InitStruct.Mode      = GPIO_MODE_OUTPUT_PP;
-        GPIO_InitStruct.Pull      = GPIO_NOPULL;
-
-        /* LCD_ON Pin configuration */
-        GPIO_InitStruct.Pin = GPIO_PIN_6;
-        HAL_GPIO_Init(GPIOK, &GPIO_InitStruct);
-
-        /* LCD_CS Pin configuration */
-        GPIO_InitStruct.Pin = GPIO_PIN_12;
+        GPIO_InitStruct.Speed     = GPIO_SPEED_HIGH;
+        GPIO_InitStruct.Pin       = GPIO_PIN_12;
         HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+        HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_SET);
+
+        /* DISP_DC pin configuration (general output GPIO) */
+        GPIO_InitStruct.Pin       = GPIO_PIN_5;
+        HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
+        HAL_GPIO_WritePin(GPIOI, GPIO_PIN_5, GPIO_PIN_RESET);
+
+        /* DISP_RESET pin configuration (general output GPIO) */
+        GPIO_InitStruct.Pin       = GPIO_PIN_6;
+        HAL_GPIO_Init(GPIOK, &GPIO_InitStruct);
+        HAL_GPIO_WritePin(GPIOK, GPIO_PIN_6, GPIO_PIN_RESET);
+
+        /* DISP_BUSY GPIO pin configuration (general output GPIO) */
+        GPIO_InitStruct.Mode      = GPIO_MODE_INPUT;
+        GPIO_InitStruct.Pull      = GPIO_NOPULL;
+        GPIO_InitStruct.Speed     = GPIO_SPEED_HIGH;
+        GPIO_InitStruct.Pin       = GPIO_PIN_4;
+        HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
 
-        /*##-3- Configure the NVIC for SPI #########################################*/
         /* NVIC for SPI */
         HAL_NVIC_EnableIRQ(SPI2_IRQn);
+    } else if (hspi->Instance == SPI5) {
+        /* SPI5
+         * PF6 SPI5_NSS
+         * PF7 SPI5_SCK
+         * PF8 SPI5_MISO
+         * PF9 SPI5_MOSI
+         */
+        __HAL_RCC_GPIOF_CLK_ENABLE();
+        __HAL_RCC_SPI5_CLK_ENABLE();
+        gpio_config(GPIO_SPI5_SCK,  GPIO_STM32_AF | GPIO_STM32_AFn(GPIO_AF5_SPI5) | GPIO_PULLUP);
+        gpio_config(GPIO_SPI5_MISO, GPIO_STM32_AF | GPIO_STM32_AFn(GPIO_AF5_SPI5) | GPIO_PULLUP);
+        gpio_config(GPIO_SPI5_MOSI, GPIO_STM32_AF | GPIO_STM32_AFn(GPIO_AF5_SPI5) | GPIO_PULLUP);
+        HAL_NVIC_EnableIRQ(SPI5_IRQn);
     }
 }
 

target/dartuinoP0/rules.mk

@@ -9,6 +9,7 @@ PLATFORM := stm32f7xx
 SDRAM_SIZE := 0x00800000
 SDRAM_BASE := 0xc0000000
 
+DISPLAY_PANEL_TYPE ?= LS013B7DH06
 GLOBAL_DEFINES += \
     ENABLE_UART3=1 \
     ENABLE_SDRAM=1 \
@@ -28,6 +29,7 @@ GLOBAL_INCLUDES += $(LOCAL_DIR)/include
 
 MODULE_SRCS += \
     $(LOCAL_DIR)/init.c \
+	$(LOCAL_DIR)/display/eink.c \
     $(LOCAL_DIR)/sensor_bus.c \
     $(LOCAL_DIR)/usb.c \
 
@@ -37,11 +39,8 @@ MODULE_DEPS += \
 
 ifneq ($(DISPLAY_PANEL_TYPE),)
 
-MODULE_SRCS += \
-    $(LOCAL_DIR)/memory_lcd.c
-
 GLOBAL_DEFINES += \
-    ENABLE_LCD=1
+    ENABLE_LCD=0
 
 endif
 

target/dartuinoP0/sensor_bus.c

@@ -23,12 +23,12 @@
 #include <err.h>
 #include <kernel/mutex.h>
 #include <platform/gpio.h>
+#include <platform/spi.h>
 #include <target/gpioconfig.h>
 #include <target/bmi055.h>
 #include <target/sensor_bus.h>
 #include <dev/accelerometer.h>
 
-static mutex_t sensorbus_mutex;
 static SPI_HandleTypeDef spi_handle;
 
 static uint8_t tx_buff[16];
@@ -49,19 +49,7 @@ status_t acc_read_xyz(position_vector_t *pos_vector_p)
 
 status_t acc_flush(uint8_t *tbuff, uint8_t *rbuff, uint8_t numbytes)
 {
-    status_t ret_status;
-
-    mutex_acquire(&sensorbus_mutex);
-
-    gpio_set(GPIO_ACC_nCS,GPIO_PIN_RESET);
-
-    ret_status = HAL_SPI_TransmitReceive(&spi_handle, tbuff, rbuff, numbytes, 5000);
-
-    gpio_set(GPIO_ACC_nCS,GPIO_PIN_SET);
-
-    mutex_release(&sensorbus_mutex);
-
-    return ret_status;
+    return spi_transaction(&spi_handle, tbuff, rbuff, numbytes, GPIO_ACC_nCS);
 }
 
 /**
@@ -71,11 +59,6 @@ status_t acc_flush(uint8_t *tbuff, uint8_t *rbuff, uint8_t numbytes)
 status_t sensor_bus_init_early(void)
 {
     __HAL_SENSOR_BUS_GPIO_CLK_ENABLE();
-    __HAL_RCC_SPI5_CLK_ENABLE();
-
-    gpio_config(GPIO_SPI5_SCK,  GPIO_STM32_AF | GPIO_STM32_AFn(GPIO_AF5_SPI5) | GPIO_PULLUP);
-    gpio_config(GPIO_SPI5_MISO, GPIO_STM32_AF | GPIO_STM32_AFn(GPIO_AF5_SPI5) | GPIO_PULLUP);
-    gpio_config(GPIO_SPI5_MOSI, GPIO_STM32_AF | GPIO_STM32_AFn(GPIO_AF5_SPI5) | GPIO_PULLUP);
 
     gpio_config(GPIO_NRF_CS,    GPIO_OUTPUT );
     gpio_config(GPIO_NRF_INT,   GPIO_INPUT   | GPIO_PULLUP);
@@ -103,17 +86,14 @@ status_t sensor_bus_init_early(void)
     spi_handle.Init.NSS               = SPI_NSS_SOFT;
     spi_handle.Init.Mode              = SPI_MODE_MASTER;
 
-    if (HAL_SPI_Init(&spi_handle) != HAL_OK) {
+    if (spi_init(&spi_handle) != HAL_OK) {
         return ERR_GENERIC;
     }
     return NO_ERROR;
 }
 
-
-
 void sensor_bus_init(void)
 {
-    mutex_init(&sensorbus_mutex);
 }
 
 

target/stm32f746g-disco/rules.mk

@@ -25,6 +25,7 @@ GLOBAL_DEFINES += \
 MODULE_SRCS += \
     $(LOCAL_DIR)/init.c \
     $(LOCAL_DIR)/lcd.c \
+    $(LOCAL_DIR)/spi.c \
     $(LOCAL_DIR)/usb.c
 
 MODULE_DEPS += \