lby/lk
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
1,660 Commits 39 Branches 0 Tags
f2430462b6adc5ccabb85614b1d680ad85fba120
Commit Graph

354 Commits

Author SHA1 Message Date
Travis Geiselbrecht
dd29481ba0 [arch][arm-m] set target debug led 1 when inside irq handler 2015-12-14 15:20:25 -08:00
Travis Geiselbrecht
75fb9e7f26 [arch][mips] allow the platform to select a particular mips implementation 2015-12-08 14:20:37 -08:00
Travis Geiselbrecht
a0e342dbbd [arch][mips] configure the timer more generically 2015-12-04 18:53:24 -08:00
Travis Geiselbrecht
74a522b5b2 [arch][mips] learned about the la pseudo opcode 2015-12-02 19:38:30 -08:00
Travis Geiselbrecht
434f7b12f6 [arch][mips] get the architectural timer working 2015-12-02 18:34:43 -08:00
Travis Geiselbrecht
38a5e7bd4f WIP more work on mip 
got interrupts working
started work on timer
 2015-12-01 19:19:23 -08:00
Travis Geiselbrecht
cd5ac2f34e WIP mips: first semi-functional mips port 
Context switches work, console alive. No interrupts.
 2015-12-01 01:05:37 -08:00
Travis Geiselbrecht
f5ff5fcfd3 WIP: mips32 on qemu 2015-11-30 18:57:37 -08:00
Zhu, Bing
6216532654 [arch][x86][x64][fpu]fix compile failure when X86_WITH_FPU is not defined. 
With this patch, no compile failure issue when either X86_WITH_FPU not defined
or defined as 0(1).

Signed-off-by: Zhu, Bing <bing.zhu@intel.com>
 2015-11-25 13:36:04 -08:00
Travis Geiselbrecht
4ab14424bd [cppcheck] clean up a few suggestions from cppcheck 2015-11-24 15:08:38 -08:00
Travis Geiselbrecht
b822b1f64f [arch][arm] fix the stack usage script to take pre-c++ unmangled dissassembly 
The unmangled dissassembly was fouling up the symbol matcher regular expression.
Easier to just process manged symbols and unmangle it later.
 2015-11-13 13:20:13 -08:00
Zhu, Bing
9f086cb53a [arch][x86_64][fpu]use correct initial fpu states when each thread is created 
Currently, all new thread created with zero fpu states (512byte buffer of
fxsave area is filled up with 0s), then when a new thread triggers "fpu
device not avialbe" exception (lazy fpu algorithm) at the first time, the
handler just blindly call fxrstor to fetch all those zero states from fxsave
area buffer. This patch is just to guarantee each new thread to have correct
inital fpu states.

Note that x86 fpu code isn't changed in this patch because the 32/64 bit
fpu code are 99% duplicated. I assume that they should be merged in future.

Signed-off-by: Zhu, Bing <bing.zhu@intel.com>
 2015-11-12 14:44:22 -08:00
Travis Geiselbrecht
6a9df9aaed [arch][arm] mass reformat all files to space indention 
Used scripts/codestyle.space on .c and .h files
Manually converted .S files
 2015-11-09 14:34:29 -08:00
Zhu, Bing
b6647f5bef [arch][x86][fpu]Change naming convention for FPU flag 
To align with lk/arm flag naming convention, FPU flag
ENABLE_FPU is changed to X86_WITH_FPU

Signed-off-by: Zhu, Bing <bing.zhu@intel.com>
 2015-11-09 22:14:11 +08:00
Travis Geiselbrecht
9c69b36411 [arch][microblaze] fix the microblaze port 
Apparently stumbled into some sort of linker bug with gc-sections enabled.
Disable for now, and clean up the linker script a little bit.
 2015-11-07 02:48:05 -08:00
Travis Geiselbrecht
853c436ea3 [arch][x86] mass-reformat to space indents on all the x86 and x86-64 files 
used scripts/codestyle.space
 2015-11-06 19:32:51 -08:00
Travis Geiselbrecht
e189cd3223 [arch][x86-64] clean up the context switch code to only save required registers 
-Move the guts into a separate asm fileto clean up the fake return hack.
 2015-11-06 19:32:51 -08:00
Travis Geiselbrecht
64fe297cb5 [arch][x86] fix multiboot to properly just cover the data segment, fix x86-64 bug 
-Add -6 switch to do-qemux86 to build and run the x86-64 target
-Fix bug in x86-64 context switch, do not understand how it ever worked.
 2015-11-06 19:32:51 -08:00
Travis Geiselbrecht
121d0b603b [arch] tighten up linker scripts to make sure the section sentinels cover just what they need 2015-11-06 19:32:51 -08:00
Bing Zhu
60c8eb2e56 [arch][x86_64][mmu] fix virtual addr and physical addr validity check 
Canonical address is meaningful only for VIRTUAL address, for physical
address, just check max supported address reported by CPUID capability.
 2015-11-05 16:52:03 -08:00
Travis Geiselbrecht
7980df73b5 [arch][or1k] fix the or1k port 2015-10-28 11:05:36 -07:00
Travis Geiselbrecht
2c52edce0b [app][tests] set ENABLE_FPU in arch/x86 targets, enable floating point tests 2015-10-27 13:19:07 -07:00
Travis Geiselbrecht
d394f5b83f [arch][x86] fix a few warnings in x86 code 2015-10-27 13:17:50 -07:00
yu-cheng yu
0400a04945 [arch][x86] This is floating point support for intel x86 and x86-64. 
Change-Id: Id0b0e2b69c1d27832eb656935e944c04681b324a
 2015-10-27 13:04:45 -07:00
Travis Geiselbrecht
0e1ce411ba [make] add ability to set EXTRA_LINKER_SCRIPTS in modules 
This allows for individual modules to extend the main linker script,
primarily to add their own sections to interate over.
Remove the main shared_* linker scripts.
 2015-10-26 16:47:18 -07:00
Travis Geiselbrecht
35ebee0e40 [merge] branch 'heapswitch' 
This picks up the major work of allowing multiple heap implementations
and enable dlmalloc as an alternate heap to the simple existing one
(now called 'miniheap').

Also added a novm page allocator for memory management on systems too small
or missing an mmu to have a vm. Not much more than a simple bitmap allocator
that the heap pulls from. Allows for other heaps and/or users of physical
memory to coexist and span multiple banks of memory.
 2015-10-20 16:53:00 -07:00
Travis Geiselbrecht
88d0001cdc [arch][arm] add lk.elf.stack to the generated list so it gets removed in the clean target 2015-10-19 19:47:29 -07:00
Travis Geiselbrecht
e58d0759ec [arch][multiple] finally solve the linker-script-not-updated problem 
If a make variable was modified in a way that would cause the linker
script to need to be regenerated on arches that use generated linker
scripts, make sure we get a fresh copy.

Reuse the same generate-then-replace logic that goes into config.h
files.
 2015-10-19 19:43:31 -07:00
Travis Geiselbrecht
3b2d7a268b [make] remove the need for a module to manually add $(LOCAL_DIR)/include to the global include path 
Pretty much every module in the system was already doing it, so do it
automatically.
 2015-10-19 19:07:16 -07:00
Travis Geiselbrecht
1485131d00 [lib][heap] refactor top level malloc/free into lib/heap 
Flatten a level by moving malloc/free/new and friends into lib/heap.
Punch realloc and a few others directly through into the underlying
heap implementation. Remove heap_alloc and heap_free entirely.
 2015-10-19 14:57:51 -07:00
Travis Geiselbrecht
7c09e82033 [make] make sure MEMBASE and MEMSIZE are always set exactly once 2015-10-15 17:22:16 -07:00
Arve Hjønnevåg
fb49e1a184 [arch][arm] Dump original svc sp and lr in fault handlers 2015-10-14 13:43:54 -07:00
Travis Geiselbrecht
3d3998eb58 [lib][console] move the panic shell test into console.h and fix a few missing debug.h includes 2015-10-12 18:26:48 -07:00
Travis Geiselbrecht
713e138de9 [arch][x86] clean up the way memory size is detected and the vm initialized 
Also fix a few warnings in arch/x86
 2015-10-11 14:09:55 -07:00
Travis Geiselbrecht
5a221c4919 [arch][x86-64] add nulled out arch_sync_cache_range 2015-10-11 12:36:04 -07:00
Travis Geiselbrecht
3d096a3e60 [merge] merge pending changes from Intel for x86 and x86-64 
Intel repo at https://github.com/srodrig1/lk
 2015-10-11 12:27:25 -07:00
Travis Geiselbrecht
2141ec6be5 [arch][x86] stub out arch_cache_sync for x86 2015-10-11 12:01:11 -07:00
Shreyas Nagaraj
d6b1ffe03f [arch][x86] Un-setting the improper flags which was being set for the pdp entries (x86 paging level) in the x86 PAE Mode 2015-10-01 23:47:44 -04:00
Travis Geiselbrecht
e41856c62b [arch][arm] add a routine to enter user space directly 2015-09-24 15:55:51 -07:00
Travis Geiselbrecht
294ded0d57 [kernel][vmm] add support for user address spaces 
Still doesn't switch between them, but allows for a separate container
of regions to be created and destroyed.
 2015-09-23 17:43:37 -07:00
M1cha
8e0afb2b5e [arch][or1k] get working after SMP changes 2015-09-20 18:20:22 -07:00
Travis Geiselbrecht
641a948c4e [arch][arm-m] add stubbed out cache routines for cortex-ms that dont have a cache 2015-09-20 13:24:22 -07:00
Travis Geiselbrecht
56e5680943 [arch][microblaze] stub out cache routines to get it compiling again 2015-09-20 13:19:40 -07:00
Travis Geiselbrecht
25cf30637f [vm] have the pmm routines return a size_t instead of uint for 64bit compatibility 2015-09-20 12:13:07 -07:00
Travis Geiselbrecht
169c743c27 [arch][arm64] allow floating point code 2015-09-20 12:13:07 -07:00
Arve Hjønnevåg
69ca5903cf [arch][arm64] Implement lazy fpu/simd state loading 
If the fpu/simd registers on this cpu were last used by the current
thread and the current thread last used the fpu/simd register on the
current cpu, then the load can be skipped.

We still always save the state, to avoid a situation where a cpu wants
to run a thread where the fpu/simd register state for that thread is
only available in the registers of another cpu.

Change-Id: I062aa0792180b9ec08a5dd95b5f4f6ba165167e1
 2015-09-20 12:13:07 -07:00
Arve Hjønnevåg
5ab22dee7f [arch][arm64] Add fpu support 
Enable fpu registers on demand. Save and disable them on the next
context switch.

Change-Id: I5a1b98044757fd6de7405a7aff3f87b2315ba74b
 2015-09-20 12:13:07 -07:00
Travis Geiselbrecht
6e82ef9722 [arch][arm] cortex-a15 can count the number of cpus as well 2015-09-20 12:13:07 -07:00
Travis Geiselbrecht
e7e894900f [arch][arm64] get compiling again 2015-09-20 12:13:06 -07:00
Travis Geiselbrecht
0f207bbc02 [arch][arm-m] print relevant data on memmanage exceptions 2015-09-17 15:09:53 -07:00