In the case of platforms where a bios or firmware has not already
assigned all the resources, do so. Requires the platform supply one or
more ranges of physical address space and IO that can be mapped into
BARs.
Handles iterating through bridges, computing the sizes of all the
peripherals downstream and rolling that up as well.
Wire them up on arm and riscv which need them. x86-pc does not, so dont
call it.
Also fix a few miscellaneous bugs, notably PCI not detecting 64bit bars
properly due to an off by one bit error.
FDT encodes the range of available mmio and io ports that the PCI bus
can use to map bars. Return this information out of the FDT walker
helper routines to feed into the PCI bus manager in the future.
Had to rearrange the proble logic somewhat, but now the bus manager will
assign consequtive bus numbers as it finds bridges and recursively
drills down to discover the entire bus structure.
Does not assign resources yet, but need to do this in the first pass
to find all of the devices before can figure out how much space they
occupy.
This fixes an infinite recursion where it was stepped into bridge a
bridge that has the secondary bus set to 0, which caused it to start
over and probe bus 0 until it blew the stack.
Better fix is to actually assign busses.
Probe the size first, and if that turns up anything, mark the bar as
valid, even if the address is set to 0. The address can be configured in
a later pass of the bus manager.
Also print the bars on boot.
Since probing the size of a BAR requires writing and reading back from
the address field, do it at probe time and cache the data instead of at
api time. This should avoid fouling up any mmio transactions in flight.
-Add C++ header guards around the public api.
-Fix a divide by zero bug in the test console routine.
-Add a new pktbuf api to assist with resetting a pktbuf back to default
values for reuse in an ethernet driver.
-Add a bus manager level, which is an object oriented walk of the pci
busses to build a per device object for later manipulation.
-Add features to enable MSI interrupts.
-Extend generic interrupt api to allow the platform to allocate vectors
for MSI interrupts.
-Rearrange a bit of the pc platform for the platform api changes.
-Add PC platform support for using the local apic to EOI MSI vectors.
-Fix up a few existing PCI drivers for small API changes.
-Add a few stubbed out routines for non PC platforms that use PCI.
Previously would only set both UXN and PXN for no execute pages, but for
pages not marked no execute, neither bit was set. Change to mask out the
other privilege mode.
Import verbatim at fuchsia repository at commit 645dbffdfbf52f72491187a1c59af1a677e3dd00
which is the initial commit before it was more excessively converted to
fuchsia style C++.
Issue #310
