- Move a bit of the shared logic of secondary bootstrapping into a new
function, lk_secondary_cpu_entry_early() which sets the current cpu
pointer before calling the first half of the secondary LK_INIT
routines.
- Create the per cpu idle threads on the main cpu instead of the
secondary as they come up.
- Tweak all of the SMP capable architectures to use this new path.
- Move the top level mp routines into a separate file top/mp.c
- A bit more correctly ifdef out more SMP code.
Instead of setting a counter of the number of secondaries to start, have
platform or target code pass in a list of harts to start instead. This
allows for there to be discontinuties in the layout of the cpu harts, or
in the case of some sifive based hardware, hart 0 is otherwise offline.
Up until now the bottom part of ram has been identity mapped, left over
from initial bootstrapping. Set up two top level page tables: one with the
the identity map and one without. Once the kernel starts switch to the second
but keep the former around for bootstrapping secondary cpus.
Start adding support for user address spaces, currently mostly untested.
Still have to solve the problem of keeping the kernel parts of the page tables
in sync. Will probably preallocate all of the ones needed.
-Add support for probing SBI extensions
-Switch to newer versions if present
-Add HBM extension which allows proper secondary cpu bootstrap
-Add support for secondary bootup via HBM.
Turns out that in some cases we can't really rely on a particular boot cpu id
so go ahead and simply dynamically assign cpu numbers by having each cpu
increment an atomic number in the very top of start.S. The first one in gets
the worm.
Now you need to include arch/atomic.h to get to the atomic routines.
This simplifies a recusion issue in the way arch/ops.h included
arch_ops. Also just generally makes things cleaner.
Add a define that sets the maximum allowed hart number, potentially
higher than the maximum number of allowed cpus.
This lets us more cleanly deal with having a higher HART number than the
logical cpu numbering. Only really works where it's still fairly packed
around 0, but in the case of the Sifive Unleased board it's just offset
by 1 so it's not a huge loss.
Generally clean up RISCV SMP boot code by rearranging things a bit as
well.
Add support for running LK in supervisor mode or machine mode.
- Macro-ify CSR access to use correct CSR # or use SBI call as req'd
- Add support to make SBI calls
- Split CLINT and lk timer abstraction so that RISC-V timer can use SBI
as required.
- Add support for booting other harts as primary since hart0 on U540
does not support S-mode. A map is used to get LK cpu number from
hartid.
Support mp lk start on RISC-V. Several changes throughout were required:
- Add signal in asm start to force secondary harts to wait for bss to be
cleared.
- Use mhartid in arch_curr_cpu_num, PLIC, and CLINT
- Use tp register as thread pointer instead of global variable.
- Support sending IPIs between harts using CLINT
- Add spinlock implementation
