2 Commits

Author	SHA1	Message	Date
Elliot Berman	acfe991c7f	[arch][riscv] Expose RISC-V mp kernel start ... Support mp lk start on RISC-V. Several changes throughout were required: - Add signal in asm start to force secondary harts to wait for bss to be cleared. - Use mhartid in arch_curr_cpu_num, PLIC, and CLINT - Use tp register as thread pointer instead of global variable. - Support sending IPIs between harts using CLINT - Add spinlock implementation	2020-01-16 23:06:28 -08:00
Elliot Berman	d239adf839	[arch][riscv] Add basic support for SiFive HiFive Unleashed ... Most of changes were moving around where macros were defined, plus the following: - Remove requirement for floating point on RV64 to support booting monitor core on U54 SoC. - Add support for Debug LEDs on HiFive Unleashed Board	2020-01-16 23:06:28 -08:00