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433 Commits

Author SHA1 Message Date
Travis Geiselbrecht
cbb6e05127 [arm-m][fpu] fix fpu context switch to not overly trigger fpused tracking 
Make sure stellaris builds with fpu enabled
 2016-03-29 00:02:54 -07:00
Travis Geiselbrecht
8550876169 [arch][arm] try to appropriately use __FPU_PRESENT and __FPU_USED 
__FPU_PRESENT is set by platform specific cmsis headers
__FPU_USED is set in the cmsis header if __FPU_PRESENT is 1 and the compiler has been
invoked with code to use the fpu.
 2016-03-28 22:19:23 -07:00
Travis Geiselbrecht
8c506eba61 [arch][arm] fix up the cortex-m fpu code to build again on all three combinations of arch/fpu 
cortex-m0 with no fpu and limited instructions
cortex-m3+ with no fpu
cortex-m4/m7 with fpu

Untested if this still works.
 2016-03-28 19:57:17 -07:00
Travis Geiselbrecht
f92aad2622 [merge] merge master into the cortex-m fpu working branch 2016-03-28 19:09:40 -07:00
Gurjant Kalsi
44e74f0486 [dartuino][bootloader] Merge bootloader branch into master. 2016-03-28 12:05:20 -07:00
Zhu, Bing
68447dbeca [arch][x86] load initial stack pointer in boot entry 
Initially, stack pointer (esp) is undefined in multiboot protocol,
to avoid potential memory corruption, set it with defined value.

Signed-off-by: Zhu, Bing <bing.zhu@intel.com>
 2016-03-15 10:24:14 -07:00
Travis Geiselbrecht
b2583192e1 [arch][arm-m] move the armv6m vs armv7m code conditional into macros 
Arguably cleans up the code.
 2016-03-14 18:05:41 -07:00
Gurjant Kalsi
a8be9611cc [dartuino][bootloader] Get Bootloader USB working. 2016-03-09 15:23:25 -08:00
Gurjant Kalsi
1458330c8b [arch][arm-m] Implement quiesce and chain load for arm-m 2016-03-09 15:21:04 -08:00
Zhu, Bing
04dd6ec434 [arch][x86]fix compile failure in 32bit interrupt frame structure 
When PAGE_FAULT_DEBUG_INFO flag is defined, the compile will fail.
This fix is to unify the member names of interrupt frame structure
x86_iframe_t. This patch also enables pagefault debugging for 32bit

Signed-off-by: Zhu, Bing <bing.zhu@intel.com>
 2016-03-03 22:18:54 -08:00
Travis Geiselbrecht
ee672a5471 [arch][x86] flatten x86-64 and x86 into a single tree of code 
Major refactor of x86 code into a single arch.
Also bump both 32 and 64 bit to running the kernel at a 'high' address.
 2016-02-29 12:42:45 -08:00
Travis Geiselbrecht
c705e4d0ff [arch][arm64] add multi-aspace and general bugfixes to arm64 2016-02-23 21:07:17 -08:00
Travis Geiselbrecht
171d14c751 [arch][arm] move CMSIS into external/ 2016-02-20 11:31:51 -08:00
Travis Geiselbrecht
14a4c60172 [kernel][vm] get rid of external declaration of address_to_page 2016-02-16 15:25:31 -08:00
Travis Geiselbrecht
9a5cd5c529 [kernel][vm] add support for multiple user address spaces 
Generically add support for more than one user address space,
attach to a thread, and context switch as thread swaps happen.

Add support for ARM and ARM64, and stub out support for x86 platforms.
 2016-02-16 15:24:25 -08:00
Travis Geiselbrecht
a4ca0a6e00 [vmm] move most users of arch_mmu_query directly to vaddr_to_paddr() 2016-02-14 12:45:53 -08:00
Travis Geiselbrecht
d569c090ea [vim] remove vim expandtab comments on most of the files 2016-02-14 12:32:07 -08:00
Travis Geiselbrecht
2eb32a4369 [style] mass reformat all the non external code to 4 space indents 
Ran everything through scripts/codestyle.space, which uses astyle
to generally follow K&R style.

Biggest non whitespace change is pulling brackets down on function
declarations, which I'm pretty ambivalent about, but astyle insists
on taking a stance
 2016-02-14 12:24:01 -08:00
Arve Hjønnevåg
6e4165431f [arch][arm64] Add a dsb to context switch on smp system. 
Fixes a crash where a thread would get preempted and move to another
cpu before executing the dsb in arm64_mmu_unmap. This would leave the
old mapping in the tlb, since the cpu that executed the dsb did not
have any pending tlb maintenance operations.

Change-Id: I3753d7020f983672966c125d8010f5f4f7c46ed1
 2016-02-12 09:11:45 -08:00
Michael Ryleev
4299604eab [arch][arm64] Access .Lpage_tables_not_ready variable as int 
Underlying issue is that any unaligned access executed before mmu is ON
would generates alignment fault regardless of the state of alignment fault
control bit of SCTLR register.

Change-Id: Icf8c533d3388e38669179572fcbb9397b573e9ed
 2016-02-08 13:14:43 -08:00
Michael Ryleev
7cdc7dc68f [arch][arm64] Remove unused variable 
Change-Id: I9f36092a938642f96c9a8488e4fb35017be40f9d
 2016-02-08 13:14:27 -08:00
Gurjant Kalsi
09dbf477df [cmsis][patch][irq] Patch file for changes to code that we don't own. 2016-01-29 17:35:08 -08:00
Gurjant Kalsi
056d6aada3 [arm-m][irq][systick] Don't change the systick priority inside arm/systick. All interrupts should be the same priority to avoid nested interrupts which are unsupported by LK. 2016-01-29 17:34:58 -08:00
Travis Geiselbrecht
4ae7e40331 [arch][arm64] only try to restore fpu state if the per cpu thread register is set 
This fixes a bug in early init when a secondary cpu uses the fpu unit
before the thread local register is set.
 2016-01-27 19:16:03 -08:00
nqbit
dd8dd061b8 [arch][arm] changes to support cortex-m0plus architecture 2016-01-18 11:07:31 -08:00
Eric Holland
3d7e1f4968 [arch][arm] changes to support cortex-m0 architecture 2016-01-17 17:35:06 -08:00
Travis Geiselbrecht
dd29481ba0 [arch][arm-m] set target debug led 1 when inside irq handler 2015-12-14 15:20:25 -08:00
Travis Geiselbrecht
75fb9e7f26 [arch][mips] allow the platform to select a particular mips implementation 2015-12-08 14:20:37 -08:00
Travis Geiselbrecht
a0e342dbbd [arch][mips] configure the timer more generically 2015-12-04 18:53:24 -08:00
Travis Geiselbrecht
74a522b5b2 [arch][mips] learned about the la pseudo opcode 2015-12-02 19:38:30 -08:00
Travis Geiselbrecht
434f7b12f6 [arch][mips] get the architectural timer working 2015-12-02 18:34:43 -08:00
Travis Geiselbrecht
38a5e7bd4f WIP more work on mip 
got interrupts working
started work on timer
 2015-12-01 19:19:23 -08:00
Travis Geiselbrecht
cd5ac2f34e WIP mips: first semi-functional mips port 
Context switches work, console alive. No interrupts.
 2015-12-01 01:05:37 -08:00
Travis Geiselbrecht
f5ff5fcfd3 WIP: mips32 on qemu 2015-11-30 18:57:37 -08:00
Zhu, Bing
6216532654 [arch][x86][x64][fpu]fix compile failure when X86_WITH_FPU is not defined. 
With this patch, no compile failure issue when either X86_WITH_FPU not defined
or defined as 0(1).

Signed-off-by: Zhu, Bing <bing.zhu@intel.com>
 2015-11-25 13:36:04 -08:00
Travis Geiselbrecht
4ab14424bd [cppcheck] clean up a few suggestions from cppcheck 2015-11-24 15:08:38 -08:00
Travis Geiselbrecht
b822b1f64f [arch][arm] fix the stack usage script to take pre-c++ unmangled dissassembly 
The unmangled dissassembly was fouling up the symbol matcher regular expression.
Easier to just process manged symbols and unmangle it later.
 2015-11-13 13:20:13 -08:00
Zhu, Bing
9f086cb53a [arch][x86_64][fpu]use correct initial fpu states when each thread is created 
Currently, all new thread created with zero fpu states (512byte buffer of
fxsave area is filled up with 0s), then when a new thread triggers "fpu
device not avialbe" exception (lazy fpu algorithm) at the first time, the
handler just blindly call fxrstor to fetch all those zero states from fxsave
area buffer. This patch is just to guarantee each new thread to have correct
inital fpu states.

Note that x86 fpu code isn't changed in this patch because the 32/64 bit
fpu code are 99% duplicated. I assume that they should be merged in future.

Signed-off-by: Zhu, Bing <bing.zhu@intel.com>
 2015-11-12 14:44:22 -08:00
Travis Geiselbrecht
09acdf8afe WIP arm-m fpu 2015-11-11 18:07:07 -08:00
Travis Geiselbrecht
6475660350 WIP checkpoint 2015-11-11 13:22:07 -08:00
Travis Geiselbrecht
420c557c6e WIP fpu bits 2015-11-09 16:30:16 -08:00
Travis Geiselbrecht
6a9df9aaed [arch][arm] mass reformat all files to space indention 
Used scripts/codestyle.space on .c and .h files
Manually converted .S files
 2015-11-09 14:34:29 -08:00
Zhu, Bing
b6647f5bef [arch][x86][fpu]Change naming convention for FPU flag 
To align with lk/arm flag naming convention, FPU flag
ENABLE_FPU is changed to X86_WITH_FPU

Signed-off-by: Zhu, Bing <bing.zhu@intel.com>
 2015-11-09 22:14:11 +08:00
Travis Geiselbrecht
9c69b36411 [arch][microblaze] fix the microblaze port 
Apparently stumbled into some sort of linker bug with gc-sections enabled.
Disable for now, and clean up the linker script a little bit.
 2015-11-07 02:48:05 -08:00
Travis Geiselbrecht
853c436ea3 [arch][x86] mass-reformat to space indents on all the x86 and x86-64 files 
used scripts/codestyle.space
 2015-11-06 19:32:51 -08:00
Travis Geiselbrecht
e189cd3223 [arch][x86-64] clean up the context switch code to only save required registers 
-Move the guts into a separate asm fileto clean up the fake return hack.
 2015-11-06 19:32:51 -08:00
Travis Geiselbrecht
64fe297cb5 [arch][x86] fix multiboot to properly just cover the data segment, fix x86-64 bug 
-Add -6 switch to do-qemux86 to build and run the x86-64 target
-Fix bug in x86-64 context switch, do not understand how it ever worked.
 2015-11-06 19:32:51 -08:00
Travis Geiselbrecht
121d0b603b [arch] tighten up linker scripts to make sure the section sentinels cover just what they need 2015-11-06 19:32:51 -08:00
Bing Zhu
60c8eb2e56 [arch][x86_64][mmu] fix virtual addr and physical addr validity check 
Canonical address is meaningful only for VIRTUAL address, for physical
address, just check max supported address reported by CPUID capability.
 2015-11-05 16:52:03 -08:00
Travis Geiselbrecht
7980df73b5 [arch][or1k] fix the or1k port 2015-10-28 11:05:36 -07:00