Most of changes were moving around where macros were defined, plus the
following:
- Remove requirement for floating point on RV64 to support booting
monitor core on U54 SoC.
- Add support for Debug LEDs on HiFive Unleashed Board
* Adds target tms570-launchpad, for TI TMS570 Launchpad Dev Kit
(https://www.ti.com/store/ti/en/p/product/?p=LAUNCHXL2-TMS57012)
* Adds CPU definitions for Cortex R4F (BE) CPU, implementing
ARMv7-R ISA. Does not yet add definitions for ARMv7 arch entry
functions.
* Board does not yet build - platform.c/uart.c are empty, no GIC
entry points provided.
Tweak the novm allocator to let us more easily add a variable sized
arena at boot.
Also added code to trap secondary cpus and reenable the use of WFI
instruction.
Very little needed to port except to conditionalize some assembly in the
context switch and exception code. Mostly needed to move build system
stuff around and add a new project.
The virt machine is a generic target, much like the arm virt machine.
Intended to be simple to use and a good target to run large systems like
linux on. At the moment simply support booting and simple uart and timer
support.
TL;DR most uses of lib/console.h -> lk/console_cmd.h
Move the part that lets a piece of code somewhere in the system to
define a console command from the actual lib/console api to start an
instance of the console. Move in almost every place the user of the
console command definition to the new header, lk/console_cmd.h which is
always in the include path.
Also remove most uses of testing for WITH_LIB_CONSOLE since you can
almost always just safely define it and then let the linker remove it.
Examples are include/platform.h -> platform/include/platform.h
include/target.h -> target/include/target.h
The old model generally considered these to be Always There includes,
but they're starting to stick out more and more so may as well actually
follow the model that most of the rest of the system follows.
Almost nothing changes here except moving braces to the same line as the
function declaration. Everything else is largely whitespace changes and
a few dangling files with tab indents.
See scripts/codestyle
-added support for bringing up the clocks and setting up the gpio bits
before starting the uart.
-add a proper target init routine
-add scripts to flash board via openocd
-fixed bug in riscv interrupt save state where it wasn't saving mstatus
on irq entry.
-comment out cycle enabling, not implemented on this core
-Add support for x86 legacy mode, designed for 386+ instead of pentium+
-Fixup uart driver to support com2
-Stub out PCI driver properly
-Fixup IDE driver to detect legacy disks
Currently targets qemu's sifive_e machine, which is a split flash/ram
machine, much like the Sifive HiFive1. Untested as of yet on a real
HiFive1.
Basic support including interrupts and architectural timers in place.
After a TLBI instruction the right thing to do is to execute DSB
followed by ISB. DSB ensures that the TLBI is seen by all observers of
the system and ISB ensures that the DSB has finished before continuing.
Also, the value in <Rt> is ignored for a TLBIALL. It isn't needed to
load 0 to r12 and then use r12 in the instruction. In order not to cause
confusion it is better to not load anything to r12.
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
After a TLBI instruction the right thing to do is to execute DSB
followed by ISB. DSB ensures that the TLBI is seen by all observers of
the system and ISB ensures that the DSB has finished before continuing.
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Most of the warnings are new, such as needing to mark fallthroughs on
cases explicitly. A few are based on signed vs unsigned comparisons.
Disable one warning that was annoying about comparing null to arguments
marked nonnull.
LK supports 4K page table only when update mapping.
At boot stage, 2M page used for kernel area space. And this mapping will
be updated when allocating region if region size is smaller than 2M,
this 2M page should be updated to 2M page directory, and then update 4K
pages resides in this 2M directory.
1. Update TSS selector description.
2. Enlarge TSS selector up to SMP_MAX_CPUS.
3. Enlarge interrupt numbers support to 0xFF in arch x86-64.
Signed-off-by: Zhong,Fangjian <fangjian.zhong@intel.com>
In 64-bit mode, the TSS descriptor is expanded to 16 bytes.
Currently, high 32-bit of TSS base address is set to be zero.
Updte descriptor structure definition, add high 32-bit high adress
and reserved bit.
Signed-off-by: Zhong,Fangjian <fangjian.zhong@intel.com>
