Commit Graph

626 Commits

Author SHA1 Message Date
Travis Geiselbrecht
de29964f7c [platform][zynq] tweak to build at lower optimization levels
For some reason this particular sequence isn't picked up as a warning
unless you're compiling with -O1 or below.
2020-05-16 14:29:21 -07:00
Travis Geiselbrecht
95cf798c83 [console][panic] slight tweak to where the panic shell define is set
Tweak the default platform_halt to idle the core if fully wedged.
2020-05-10 20:03:31 -07:00
Travis Geiselbrecht
7c9906a5ff [arch][riscv] Initial implementation of MMU for RISC-V
Implements both SV39 and SV48. No 32bit support yet.

Currently implements basic setup of paging in start.S by mapping a large
chunk of memory into both an identity map and to the bottom of the
kernel address space. Run the kernel out of this physical mapping.

Added basic arch mmu support for querying existing paging structures and
mapping 4K pages. No unmap support as of yet.

System boots with mmu on when running supervisor test on qemu. Untested
on real hardware as of yet.
2020-05-10 17:09:48 -07:00
Travis Geiselbrecht
89cdb26d5b [platform][arm/riscv][virt] update both arm-virt and riscv-virt to use libfdtwalk
No real change except moving fdt walking code into the fdtwalk library.

Also update some constants for ARM virt and bump the load address to
make sure the FDT works. Turns out it had been missing for a while so it
was actually not finding it because the kernel was loaded too close to
the start of memory.
2020-04-25 18:46:57 -07:00
Travis Geiselbrecht
dc1cfc0b33 [target][sifive-unleashed] get working on a physical sifive unleashed
Only tested with SBI and supervisor mode, but that's all I have now.

Add checked in copies of the device tree needed for a uboot uimage
needed to start it.
2020-03-28 20:33:04 -07:00
Travis Geiselbrecht
e0cdfbae17 [python] fix a few of the python tools to be python 2 and 3 compatible 2020-03-08 16:39:15 -07:00
Travis Geiselbrecht
a44bc7863d [dev][bus][pci] move the pci driver out of platform/pc into generic space
No functional change.
2020-03-07 18:17:36 -08:00
Travis Geiselbrecht
7648ca09d9 [platform][qemu-riscv] add virtio to bring it up to par with arm virt machine 2020-01-19 16:17:34 -08:00
Travis Geiselbrecht
0ec24d0b29 [dev][virtio] add no kernel VM workaround
Also add stride to the mmio detect routine. Not all virtio apertures are
tightly packed as they are on arm.
2020-01-19 16:15:58 -08:00
Travis Geiselbrecht
9c71a0ec57 [platform][qemu-riscv] Fixup qemu-riscv target
-Fix plic driver to handle machine vs supervisor mode
-Add switch to scripts/do-qemuriscv to run in supervisor mode (with OpenSBI)
-Use the FDT to detect the number of cpus and size of memory
2020-01-19 14:48:25 -08:00
Travis Geiselbrecht
90dc9e50ef [platform][sifive-e] get the hifive1 hardware working again
Had rotted a bit. Had to reimplement a few tweaks.
Also generally #if out a lot of the SMP code when unused on riscv.
2020-01-18 18:39:07 -08:00
Elliot Berman
acfe991c7f [arch][riscv] Expose RISC-V mp kernel start
Support mp lk start on RISC-V. Several changes throughout were required:
- Add signal in asm start to force secondary harts to wait for bss to be
  cleared.
- Use mhartid in arch_curr_cpu_num, PLIC, and CLINT
- Use tp register as thread pointer instead of global variable.
- Support sending IPIs between harts using CLINT
- Add spinlock implementation
2020-01-16 23:06:28 -08:00
Elliot Berman
d239adf839 [arch][riscv] Add basic support for SiFive HiFive Unleashed
Most of changes were moving around where macros were defined, plus the
following:
- Remove requirement for floating point on RV64 to support booting
  monitor core on U54 SoC.
- Add support for Debug LEDs on HiFive Unleashed Board
2020-01-16 23:06:28 -08:00
Venkatesh Srinivas
128890f8a8 [platform][tms570-launchpad] Skeleton of port to TI LaunchXL2-TMS57012
* Adds target tms570-launchpad, for TI TMS570 Launchpad Dev Kit
(https://www.ti.com/store/ti/en/p/product/?p=LAUNCHXL2-TMS57012)

* Adds CPU definitions for Cortex R4F (BE) CPU, implementing
  ARMv7-R ISA. Does not yet add definitions for ARMv7 arch entry
  functions.

* Board does not yet build - platform.c/uart.c are empty, no GIC
  entry points provided.
2019-11-18 15:36:28 -08:00
Travis Geiselbrecht
bff17f7e99 [platform][riscv] add code to read the size of memory from the FDT
Tweak the novm allocator to let us more easily add a variable sized
arena at boot.

Also added code to trap secondary cpus and reenable the use of WFI
instruction.
2019-11-02 18:13:02 -07:00
Travis Geiselbrecht
fdc08a8446 [arch][riscv] port to riscv64
Very little needed to port except to conditionalize some assembly in the
context switch and exception code. Mostly needed to move build system
stuff around and add a new project.
2019-11-02 17:21:13 -07:00
Travis Geiselbrecht
ae5200595c [platform][riscv-virt] added support for QEMU's riscv 'virt' machine
The virt machine is a generic target, much like the arm virt machine.
Intended to be simple to use and a good target to run large systems like
linux on. At the moment simply support booting and simple uart and timer
support.
2019-11-02 14:19:36 -07:00
Erik Gilling
4cf2997a04 [stm32f0] Update to STM32Cube v1.10.1. 2019-08-07 11:01:19 -07:00
Travis Geiselbrecht
ad246760ff [c++] remove WITH_CPP_SUPPORT flag
Just always build with it enabled.
2019-07-13 17:41:25 -07:00
Travis Geiselbrecht
6cb02526b7 [include][console] split lib/console.h into two
TL;DR most uses of lib/console.h -> lk/console_cmd.h

Move the part that lets a piece of code somewhere in the system to
define a console command from the actual lib/console api to start an
instance of the console. Move in almost every place the user of the
console command definition to the new header, lk/console_cmd.h which is
always in the include path.

Also remove most uses of testing for WITH_LIB_CONSOLE since you can
almost always just safely define it and then let the linker remove it.
2019-07-13 16:56:33 -07:00
Travis Geiselbrecht
35a8d555a3 [include] move almost all of the remainder of top level includes into a subdir
Examples are include/platform.h -> platform/include/platform.h
include/target.h -> target/include/target.h

The old model generally considered these to be Always There includes,
but they're starting to stick out more and more so may as well actually
follow the model that most of the rest of the system follows.
2019-07-13 16:09:27 -07:00
Travis Geiselbrecht
3aecdda231 [includes] replace header guards with #pragma once 2019-07-13 15:46:16 -07:00
Travis Geiselbrecht
cba9e47987 [license] replace the longer full MIT license with a shorter one
Used scripts/replacelic. Everything seems to build fine.
2019-07-05 17:22:23 -07:00
Travis Geiselbrecht
3699e45942 [include][lib] move most of the dangling top level include/lib/.h files into their lib
Only remaining one is console.h which is a little funny and will need to
be dealt with separately.
2019-06-19 22:44:15 -07:00
Travis Geiselbrecht
d8fa82cb91 [formatting] run everything through codestyle
Almost nothing changes here except moving braces to the same line as the
function declaration. Everything else is largely whitespace changes and
a few dangling files with tab indents.

See scripts/codestyle
2019-06-19 21:02:24 -07:00
Travis Geiselbrecht
1b7a28efb8 [include][lk] fixup lk/ include path move 2019-06-19 19:46:11 -07:00
Martin Foo
b66bd3e420 Add STM32F429I-DISCO1 support(default serial:USART1). 2019-06-19 18:18:52 -07:00
Travis Geiselbrecht
4148863969 [platform][qemu-virt] rename to qemu-virt-arm
Makes space for a new platform using the virt machine in qemu on another
architecture.
2019-03-30 19:46:30 -07:00
Erik Gilling
dcfd291dd2 [stm32f0xx][i2c] Add ability to override TIMINGR. 2019-03-11 15:10:40 -07:00
Travis Geiselbrecht
63be190d8b [target][sifive-e] Get LK working on a Sifive Hifive1 board
-added support for bringing up the clocks and setting up the gpio bits
before starting the uart.
-add a proper target init routine
-add scripts to flash board via openocd
-fixed bug in riscv interrupt save state where it wasn't saving mstatus
on irq entry.
-comment out cycle enabling, not implemented on this core
2019-02-18 22:13:22 -08:00
Travis Geiselbrecht
a0a6b10e0b [arch][riscv32] rename the qemu target sifive-e
The initial port is really a Sifive E platform. Call it what it is and
make space for bringing up the Sifive U and virt qemu target.
2019-02-17 20:29:50 -08:00
Erik Gilling
7ca88d22b5 [stm32f0xx] Fix '072 vector table.
The STM32F072 and STM32F070 have different vector tables.  We can't
 #ifdef on the existance of the constans like PVD_IRQn because they
 are enum values.  Right now, since we only have two supported variants,
 we're switching on the variant.  This will likely not scale.
2019-01-24 13:30:21 -08:00
Erik Gilling
060c82214d [stm32f0xx] Fix i2c clocks for HSI48 source. 2019-01-22 20:00:38 -08:00
Travis Geiselbrecht
4c29a608e9 [platform][pc] fix up bios32 PCI support, get pci IDE working again
-Spiff up the device driver starting logic to allow for statically
started devices, instead of always automatic.
2018-12-31 16:47:32 -08:00
Travis Geiselbrecht
1fbb67228d [platform][pc] get working on legacy 386 PC
-Add support for x86 legacy mode, designed for 386+ instead of pentium+
-Fixup uart driver to support com2
-Stub out PCI driver properly
-Fixup IDE driver to detect legacy disks
2018-12-30 21:08:58 -08:00
Eric Holland
be72298b9c [nrf][timer] fix bug in hires 2018-12-19 16:05:09 -05:00
Travis Geiselbrecht
f98cef7992 [warnings] fix warnings across the entire code base
Fix or squelch all warnings in all code covered by buildall.
2018-12-16 17:33:22 -08:00
Travis Geiselbrecht
8cf28bbdcf [arch][riscv] Initial port to a riscv32 sifive target
Currently targets qemu's sifive_e machine, which is a split flash/ram
machine, much like the Sifive HiFive1. Untested as of yet on a real
HiFive1.

Basic support including interrupts and architectural timers in place.
2018-12-16 16:44:23 -08:00
Eric Holland
81f50225ac [nrf][timer] improve time keeping in RTC
Improve accuracy of current_time and current_time_highres.
2018-12-13 20:47:50 -08:00
Travis Geiselbrecht
17598a2845 [platform][mt6735] fix build 2018-05-26 22:23:34 -07:00
Macpaul Lin
27425305fc [platform][mediatek][common] change default gic controller
According to source release repository of AP7350 (MT6735).
        http://git.huayusoft.com/tomsu/AP7350_MDK-kernel
        https://github.com/alexgoussev/AP7350_MDK-kernel

The common gic controller driver could not adapted to platform mt6735.
Hence a compile option here is needed.

Signed-off-by: Macpaul Lin <macpaul@gmail.com>
2018-05-22 00:05:46 -07:00
Macpaul Lin
5bec0e8460 [platform][mediatek] add mt6735 initial support
Support MT6735 platform.
Most files are copied from platform MT6797 without any modification.
The register offsets (mt_reg_base.h) were cross-referenced from the following
source code releases.
	http://git.huayusoft.com/tomsu/AP7350_MDK-kernel
	https://github.com/alexgoussev/AP7350_MDK-kernel

ToDo:
	1. Porting other peripheral drivers.
	2. Check what files can be shared between platforms
	   then reduce file duplications.

Signed-off-by: Macpaul Lin <macpaul@gmail.com>
2018-05-22 00:05:46 -07:00
Eric Holland
69963facbe [nrf52][uart] Fix but in UART init 2018-05-20 14:53:02 -07:00
Todd Eisenberger
af47d547f9 [stm32f0xx] Fix UART3/4 interrupts
The IRQ handler was being misdefined, so the correct ISR was not being
invoked.
2018-05-08 22:46:53 -07:00
Eric Holland
31b8d1d217 [nrf] Support for NRF52840 DK 2018-05-02 14:50:41 -07:00
Todd Eisenberger
e007acc4dc [stm32f0xx] Add support for stm32f070xb
This cleans up handling of a lot of optional components
across f0xx models.
2018-04-17 10:52:14 -07:00
Payam
6e05388579 [vim2] Initial support for Khadas VIM2 boards 2018-03-16 15:05:10 -07:00
Travis Geiselbrecht
5dea3e1933 [warnings] fix a few warnings introduced with newer version of gcc
Most of the warnings are new, such as needing to mark fallthroughs on
cases explicitly. A few are based on signed vs unsigned comparisons.

Disable one warning that was annoying about comparing null to arguments
marked nonnull.
2018-03-15 14:10:12 -07:00
Erik Gilling
c77f8f94bd [stm32f0xx] Enable sysconfig clock before accessing it in exti driver. 2018-02-09 15:25:12 -08:00
Todd Eisenberger
cc827a9856 [stm32f0xx] Correct register access for EXTI controller
A bunch of the register access here didn't match STM's docs.  The old
code had a few bugs:

1) The EXTI4-15 handler would clear pending bits for interrupts 16-31.
2) GPIO interrupt configuration was very misindexed.
2018-01-28 15:30:49 -08:00