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c7ce0b93610822a7bd3b44727696af8cd8ed79d8
Commit Graph

160 Commits

Author SHA1 Message Date
Travis Geiselbrecht
c7ce0b9361 [lib][display] update display_get_info to return success/failure 
Update all the users to check for error.
 2015-10-08 15:54:40 -07:00
Gurjant Kalsi
9fc8159038 [qspi][flash][bio] Added a BlockIO device / driver for the STM32f746G-Disco. 2015-10-07 15:23:34 -07:00
Carlos Pizano
065b344a7d [target][stm32f7] Enable the LCD display 
Also add the gfx library so that the gfx tests commands work.
 2015-09-22 16:40:19 -07:00
Travis Geiselbrecht
74b3827f43 [platform][vexpress-a9] remove vexpress-a9 target 
-qemu -machine virt replaces it
 2015-09-20 12:13:07 -07:00
Travis Geiselbrecht
07324bac33 [platform][foundation-emu] remove support for foundation emulator 
-qemu -machine virt replaces it
 2015-09-20 12:13:07 -07:00
Travis Geiselbrecht
861d637e8b [platform][qemu-virt] add support for -machine virt on qemu arm/aarch64 
-add a arm64 cortex-a53 based target
 2015-09-20 12:13:07 -07:00
Travis Geiselbrecht
8e4c0ac594 [platform][stm32f7xx] move mpu initialization into platform, set up inaccessible region at 0 2015-09-17 14:06:14 -07:00
Christopher Anderson
9a5589a4a4 [minip][pktbuf] Move pktbuf allocation to a common pool 
Rather than having a pool for pktbuf buffers and a pool for pktbufs, move
them to a common pool.
 2015-09-15 16:28:52 -07:00
Carlos Pizano
f053c3690b [platform][stm32f7xx] make mac address different than eval2 2015-09-11 18:01:47 -07:00
Carlos Pizano
5cb2435ea5 [platform][stm32f7xx] Wire minip for the STM32f7 disco board. 2015-09-11 18:01:47 -07:00
Carlos Pizano
7bcf5f66c5 [target][stm32f7] Configure Ethernet PHY for stm32f746g-disco 2015-09-11 18:01:47 -07:00
Carlos Pizano
b9b0d5d38a [target][stm32f746g-disco] Use correct sdram size 
The board is sold with 128 Mbit device but upon closer inspection only
64 Mbit are wired.
 2015-09-08 18:42:55 -07:00
Carlos Pizano
3ee83ae61d [target][stm32f746g-disco] Enable MPU cache configuration. 
Partial copy from stm32f7 eval2 code.
 2015-09-08 13:36:49 -07:00
Carlos Pizano
0b0b79be57 move stmf7 sdram code to /platform 
BUG=none
R=travisg@google.com

Review URL: https://codereview.chromium.org/1324223002 .
 2015-09-03 14:10:25 -07:00
Carlos Pizano
e7eeca7e65 Conditionally use HSE clock config. 
The stm32f7-discovery seems ok with the external xtal.
 2015-09-01 16:00:35 -07:00
Travis Geiselbrecht
8cf7991d47 [platform][armemu] fix up the armemu platform/target and get it building properly again 2015-09-01 13:26:27 -07:00
Travis Geiselbrecht
9118a4d605 [merge] merge from the stm32f7 branch 
Conflicts:
	arch/arm/arm-m/arch.c
 2015-08-28 15:03:17 -07:00
Travis Geiselbrecht
4a40dc2430 [platform][stm32f7xxx] move eth initialization into target space 2015-08-27 12:28:46 -07:00
Travis Geiselbrecht
7c56ee2bfa [platform][stm32f7xx] wire ethernet driver up to minip 
Enable it by default on the stm32746g-eval2 platform
 2015-08-26 17:57:27 -07:00
Travis Geiselbrecht
5d1e1a6d60 [platform][stm32f7xx] first stab at working ethernet driver 
Does nothing but receive packets and drop them on the floor. Wire up
to net stack(s) next.
 2015-08-26 17:05:44 -07:00
Carlos Pizano
dca5d73d9d New target: stm32f746-disco 
It is close to the stm32746g-eval2-test.mk however
- uart rx pin differs
- no external sram
- different lcd tech
- (possibly) different sdram config
 2015-08-24 15:33:05 -07:00
Travis Geiselbrecht
37969468f0 [target][stm32746g] switch the LCD to 565 mode and remove the extraneous flush 
Turns out gfx_flush() already calls a cache flush, the flush callback was
apparently intended to be in case you need to initiate an update to the panel.
 2015-08-21 12:00:44 -07:00
Travis Geiselbrecht
d765352674 [target][stm32746g] use the new proper cache flush api for lcd framebuffer writeback 2015-08-21 11:33:26 -07:00
Travis Geiselbrecht
462a40c597 [target][stm32746g-eval2] add cache flushing routine to lcd updates 2015-08-19 17:53:59 -07:00
Travis Geiselbrecht
dc454e719c [target][stm32746g-eval2] enable external SRAM block, update MPU cache params 
For future reference:
TEX 001 C 1 B 1 S 0 is the full cache params for cortex-m7.
 2015-08-19 17:24:30 -07:00
Carlos Pizano
fee9612b2e set heap after the lcd memory 
So that the gfx console commands don't crash LK.
 2015-08-18 14:36:32 -07:00
Travis Geiselbrecht
3967239eb7 [target][stm32746g-eval2] add MPU cache region for sdram, clear lcd on boot 2015-08-17 16:02:19 -07:00
Travis Geiselbrecht
423338d8b7 [target][stm32746g-eval2] add support for lk's display/gfx api 2015-08-17 16:02:19 -07:00
Travis Geiselbrecht
7a97739347 [target][stm32746g-eval2] add lcd initialization sequence 2015-08-17 12:33:31 -07:00
Travis Geiselbrecht
cee3576d22 [target][stm32746g-eval2] add sdram initialization sequence 2015-08-17 11:59:28 -07:00
Travis Geiselbrecht
3799cc6999 [platform][stm32f7] general cleanup of platform/target code 
-fix gpio_config, switch usart1 config to this api, move into target code
-switch to just including platform/stm32.h which gets all of the HAL apis
-redo the interrupt driven rx side of usart to be much simpler and directly
 push into the cbuf without using most of the HAL goo.
-reformat for 4 spaces
 2015-08-14 15:33:46 -07:00
Brian Swetland
54cfc1a645 [lpc43xx][gpio] implement basic gpio api, clean up header a bit 
It's hard to fully unify this without some table mapping GPIOs to PINs.
 2015-07-27 12:53:32 -07:00
Brian Swetland
a7abcb473a [target][lpclink2] lpclink2 debugger / development board 2015-07-26 23:04:37 -07:00
Brian Swetland
5747ede097 [target][lpc4337xpresso] absorb the 'generic' 43xx project 2015-07-26 12:28:10 -07:00
Travis Geiselbrecht
867782bb56 WIP STM32F7 
add rx side of uart
enable systick at proper speed
 2015-07-10 00:52:37 -07:00
Travis Geiselbrecht
94d4d499f7 WIP support for stm32f746g-eval2 board 2015-07-08 02:24:59 -07:00
Brian Swetland
b736d68903 [platform][lpc43xx] support some faster debug uart baudrates 
TARGET_DEBUG_BAUDRATE may be 115200, 1000000, 2000000, or 3000000
 2015-07-05 23:10:55 -07:00
Brian Swetland
3e3036d0c2 [platform][lpc43xx] hook up debug uart 
For the moment, just a trivial implementation in debug.c.
To be replaced with a standard lk uart "driver" later on.
 2015-07-05 05:44:54 -07:00
Brian Swetland
39afbc9668 [platform][lpc43xxx] minimal skeleton platform, target, and project 
Just enough to compile cleanly.  Not much platform-specific information
besides the IRQ numbers just yet.
 2015-07-05 05:44:54 -07:00
Brian Swetland
cbc6bb96fd [target][stm32f4-discovery] run system at 168MHz 
SYSCLK 168000000
HCLK   168000000
PCLK1  42000000
PCLK2  84000000
 2015-07-01 22:47:40 -07:00
Brian Swetland
1c3205eab1 [target][stm32f4-discovery] update to use platform/stm32f4xx 2015-06-30 23:03:02 -07:00
Travis Geiselbrecht
842cb7a7ae [warnings] fix warnings post-smp 
Most of the warnings are printf related due to lk_time_t now being defined as an
unsigned int instead of unsigned long.
 2015-06-02 21:03:05 -07:00
Travis Geiselbrecht
96ba54f187 [merge] merge back from smp branch 2015-05-28 12:52:41 -07:00
John Grossman
c2b645ef8a [zynq][gpio] Fix a collection of bugs with the GPIO driver. 
+ When setting GPIOs, the MASK_DATA registers are used.  Code was
  properly computing which register to use based on register index
  (either LSW or MSW), but was improperly computing the mask/value to
  set when the GPIO to be manipulated existed in the upper 16 bits
  (the shift needed to be offset by 16 bits and was not).
+ Do not manipulate things like the IO driver type, drive speed, and
  so on when enabling/disabling the pullup in the SLCR registers.
  Previously, whenever a GPIO was being configured, the SLCR register
  was being set to be 1.8v LVCMOS, and having the DISABLE RCV bit set.
  Things like the IO type have been set by the platform and should not
  be manipulated by the GPIO driver.  Now, the GPIO code leaves those
  bits the way they were configured, and changes only the PULLUP bit
  as well as the 4 levels mux bits (arguably, it should not even
  change the mux bits; it is the platform's job to properly mux the
  pins).
+ Address an issue with the subtle (undocumented) difference between
  the DIRM and the OEN bits when configuring for input vs. output.
  Please read the extensive comment in the code for details.

Change-Id: I160069eeef92b1cf0763274ccb64c5d14744f563
Signed-off-by: John Grossman <johngro@google.com>
 2015-05-19 10:21:33 -07:00
Arve Hjønnevåg
2c9c5959e7 Merge branch 'master' of https://github.com/travisg/lk into smp 
Change-Id: Iecb11d57b6f089234c0826932bdb229588939750
 2015-05-18 16:49:37 -07:00
Travis Geiselbrecht
580a83d74f [lib][minip] have the pktbuffers automatically allocated at startup 
Default number of buffers are 128, can be overridden with a #define.
 2015-05-02 22:48:57 -07:00
Christopher Anderson
6ef986679a [uzed] Set up pktbufs similarly to zybo 2015-04-23 13:30:39 -07:00
Christopher Anderson
4a038ceef6 [zynq] Add support for GPIO interrupts 2015-04-23 13:30:39 -07:00
Christopher Anderson
fdecb22f2e [zybo] Set yellow LED to debug led 2015-04-23 13:30:39 -07:00
Christopher Anderson
d352ac1d2b [gem][minip][pktbuf] Improvements for TX scatter gather functionality 
- GEM now supports asynchronous scatter-gather queuing and properly handling
  pktbuf ownership
- General stack cleanups in Minip
- pktbufs now grab buffers from the user, or from a preallocated pool
 2015-04-23 13:30:39 -07:00